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1. 发明申请

US20140293704A1 Auto-Suspend and Auto-Resume Operations for a Multi-Die NAND Memory Device 有权
标题翻译：多模NAND存储器件的自动挂起和自动恢复操作
公开(公告)号：US20140293704A1
公开(公告)日：2014-10-02
申请号：US13852992
申请日：2013-03-28
申请人： Ali Ghalam , Dean Nobunaga , Jason Guo
发明人： Ali Ghalam , Dean Nobunaga , Jason Guo
IPC分类号： G11C16/30
CPC分类号： G11C16/30 , G06F1/3275 , G11C5/148 , G11C8/12 , G11C16/225 , Y02D10/14
摘要： A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation.
摘要翻译：一种通过由多芯片存储器的至少一个管芯确定后续存储器操作是否为高电流存储器来控制诸如固态驱动器的多管芯存储器中的峰值电流状态的方法和装置操作，例如使能芯片的电荷泵的操作，对芯片的位线充电的操作，或编程/擦除循环操作，或其组合。如果后续存储器操作被确定为高电流存储器操作，则芯片进入暂停操作模式。响应于诸如但不限于对芯片的特定地址的命令，来自另一管芯的指示大电流存储器操作完成的恢复操作事件来恢复操作。一旦操作恢复，芯片执行高电流存储器操作。

2. 发明申请

US20110032761A1 METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE 有权
标题翻译：闪存存储器件的擦除验证方法
公开(公告)号：US20110032761A1
公开(公告)日：2011-02-10
申请号：US12909414
申请日：2010-10-21
申请人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
发明人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
IPC分类号： G11C16/16 , G11C16/04 , G11C16/34
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/3445
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
摘要翻译：公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

3. 发明授权

US07099226B2 Functional register decoding system for multiple plane operation 失效
标题翻译：功能寄存器解码系统，用于多平面操作
公开(公告)号：US07099226B2
公开(公告)日：2006-08-29
申请号：US10686401
申请日：2003-10-14
申请人： Yolanda Yuan , Jason Guo , Sai K. Tsang , Vikram Kowshik , Steven J. Schumann
发明人： Yolanda Yuan , Jason Guo , Sai K. Tsang , Vikram Kowshik , Steven J. Schumann
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1027 , G11C7/1042 , G11C7/1045
摘要： A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.
摘要翻译：用于多平面存储器的解码系统将对应于不同存储器访问操作的地址信息路由到指定的平面。该系统包括专用于随机访问读取，突发读取，编程，擦除和擦除 - 挂起程序操作的功能寄存器阵列。每个平面的平面选择器块接收所有寄存器的地址输出，平面函数选择逻辑根据指定平面的存储器访问命令控制路由。同一平面内不同类型的同时操作和嵌套操作是可能的。

4. 发明申请

US20050099857A1 Functional register decoding system for multiple plane operation 失效
标题翻译：功能寄存器解码系统，用于多平面操作
公开(公告)号：US20050099857A1
公开(公告)日：2005-05-12
申请号：US10686401
申请日：2003-10-14
申请人： Yolanda Yuan , Jason Guo , Sai Tsang , Vikram Kowshik , Steven Schumann
发明人： Yolanda Yuan , Jason Guo , Sai Tsang , Vikram Kowshik , Steven Schumann
IPC分类号： G11C7/10 , G11C8/12 , G11C7/00
CPC分类号： G11C8/12 , G11C7/1027 , G11C7/1042 , G11C7/1045
摘要： A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.
摘要翻译：用于多平面存储器的解码系统将对应于不同存储器访问操作的地址信息路由到指定的平面。该系统包括专用于随机访问读取，突发读取，编程，擦除和擦除 - 挂起程序操作的功能寄存器阵列。每个平面的平面选择器块接收所有寄存器的地址输出，平面函数选择逻辑根据指定平面的存储器访问命令控制路由。同一平面内不同类型的同时操作和嵌套操作是可能的。

5. 发明授权

US06404175B1 Multi-phase and multi-module power supplies with balanced current between phases and modules 失效
标题翻译：多相和多模块电源，具有相间和模块之间的平衡电流
公开(公告)号：US06404175B1
公开(公告)日：2002-06-11
申请号：US09757801
申请日：2001-01-09
申请人： Eric X. Yang , Jason Guo
发明人： Eric X. Yang , Jason Guo
IPC分类号： G05F1652
CPC分类号： H02M3/1584 , H02M2003/1586
摘要： A multi-phase power supply utilizes a current sensor including a sensor inductor winding connected in parallel with a filter inductor winding at the output of each phase for sensing the phase currents and balancing the current by adjusting the duty cycle of each phase through feedback control. In addition, in a multi-module power supply configuration, current between power supply modules is balanced through use of the same current sensor and current sharing technique. Each phase of the power supply includes at least one input power source and a current sensor. The sensor inductor winding and the filter inductor winding have the same number of turns and are wound about a magnetic core also present at each phase. A differential amplifier at each phase senses and amplifies any voltage difference between the outputs of the sensor inductor winding and the corresponding filter inductor winding. A current-sharing bus is formed between each of the phases, carrying the summed and averaged outputs from all the differential amplifiers. A feedback correction circuit at each phase utilizes the voltage on the current-sharing bus as a reference to control a pulse width modulator in adjusting the duty cycle of the corresponding phase, thereby balancing the load current among the phases. In a multi-module, multi-phase power supply, the current-sharing bus and a voltage-sharing bus are extended between each module and the phases of each module to achieve the same current balancing between all phases and modules.
摘要翻译：多相电源使用电流传感器，其包括与每相输出端的滤波电感器绕组并联连接的传感器电感线圈，用于通过反馈控制调节每相的占空比来感测相电流并平衡电流。另外，在多模块电源配置中，通过使用相同的电流传感器和电流共享技术来平衡电源模块之间的电流。电源的每个相包括至少一个输入电源和电流传感器。传感器电感绕组和滤波电感绕组具有相同的匝数，并缠绕在每个相位上也存在的磁芯。每个相位的差分放大器可以感测和放大传感器电感线圈和相应的滤波电感绕组的输出之间的任何电压差。在每个相之间形成一个电流共享总线，其中载有来自所有差分放大器的相加和平均的输出。每相上的反馈校正电路利用电流共享总线上的电压作为参考来控制脉冲宽度调制器来调节相应相位的占空比，从而平衡相间的负载电流。在多模块多相电源中，每个模块和各个模块的相位之间扩展了分流总线和电压共享总线，以实现所有相和模块之间的相同电流平衡。

6. 发明授权

US06215290B1 Multi-phase and multi-module power supplies with balanced current between phases and modules 有权
标题翻译：多相和多模块电源，具有相间和模块之间的平衡电流
公开(公告)号：US06215290B1
公开(公告)日：2001-04-10
申请号：US09440222
申请日：1999-11-15
申请人： Eric X. Yang , Jason Guo
发明人： Eric X. Yang , Jason Guo
IPC分类号： G05F140
CPC分类号： H02M3/1584 , H02M2003/1586
摘要： A multi-phase power supply utilizes a current sensor including a sensor inductor winding connected in parallel with a filter inductor winding at the output of each phase for sensing the phase currents and balancing the current by adjusting the duty cycle of each phase through feedback control. In addition, in a multi-module power supply configuration, current between power supply modules is balanced through use of the same current sensor and current sharing technique. Each phase of the power supply includes at least one input power source and a current sensor. The sensor inductor winding and the filter inductor winding have the same number of turns and are wound about a magnetic core also present at each phase. A differential amplifier at each phase senses and amplifies any voltage difference between the outputs of the sensor inductor winding and the corresponding filter inductor winding. A current-sharing bus is formed between each of the phases, carrying the summed and averaged outputs from all the differential amplifiers. A feedback correction circuit at each phase utilizes the voltage on the current-sharing bus as a reference to control a pulse width modulator in adjusting the duty cycle of the corresponding phase, thereby balancing the load current among the phases. In a multi-module, multi-phase power supply, the current-sharing bus and a voltage-sharing bus are extended between each module and the phases of each module to achieve the same current balancing between all phases and modules.
摘要翻译：多相电源使用电流传感器，其包括与每相输出端的滤波电感器绕组并联连接的传感器电感线圈，用于通过反馈控制调节每相的占空比来感测相电流并平衡电流。另外，在多模块电源配置中，通过使用相同的电流传感器和电流共享技术来平衡电源模块之间的电流。电源的每个相包括至少一个输入电源和电流传感器。传感器电感绕组和滤波电感绕组具有相同的匝数，并缠绕在每个相位上也存在的磁芯。每个相位的差分放大器可以感测和放大传感器电感线圈和相应的滤波电感绕组的输出之间的任何电压差。在每个相之间形成一个电流共享总线，其中载有来自所有差分放大器的相加和平均的输出。每相上的反馈校正电路利用电流共享总线上的电压作为参考来控制脉冲宽度调制器来调节相应相位的占空比，从而平衡相间的负载电流。在多模块多相电源中，每个模块和各个模块的相位之间扩展了分流总线和电压共享总线，以实现所有相和模块之间的相同电流平衡。

7. 发明授权

US07835190B2 Methods of erase verification for a flash memory device 有权
标题翻译：闪存设备的擦除验证方法
公开(公告)号：US07835190B2
公开(公告)日：2010-11-16
申请号：US12190409
申请日：2008-08-12
申请人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
发明人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
IPC分类号： G11C11/34
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/3445
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
摘要翻译：公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

8. 发明申请

US20060232303A1 Sense amplifier for flash memory device 有权
标题翻译：用于闪存设备的感应放大器
公开(公告)号：US20060232303A1
公开(公告)日：2006-10-19
申请号：US11107466
申请日：2005-04-15
申请人： Kris Li , Jason Guo , Edward Hui
发明人： Kris Li , Jason Guo , Edward Hui
IPC分类号： G01R19/00
CPC分类号： G11C7/065 , G01R19/0023 , G11C16/28
摘要： A sense amplifier circuit comprises first and second cross-coupled inverters to produce a latch with first and second power supply nodes. The first latch power supply node couples a first power supply potential to the latch when the sense amplifier is operating in a read-out mode. The second latch power supply node couples a second power supply potential to the latch when the sense amplifier operates in the read-out mode. The first and second latch power supply nodes are further configured to couple an equalization potential to the first and second power supply nodes when the latch is operating in an equalization mode.
摘要翻译：读出放大器电路包括第一和第二交叉耦合的反相器，以产生具有第一和第二电源节点的锁存器。当读出放大器在读出模式下操作时，第一锁存电源节点将第一电源电位耦合到锁存器。当读出放大器在读出模式下工作时，第二锁存电源节点将第二电源电位耦合到锁存器。第一和第二闩锁电源节点还被配置为当闩锁以均衡模式操作时将均衡电位耦合到第一和第二电源节点。

9. 发明申请

US20050078525A1 Suspend-resume programming method for flash memory 有权
标题翻译：闪存的挂起 - 恢复编程方法
公开(公告)号：US20050078525A1
公开(公告)日：2005-04-14
申请号：US10685752
申请日：2003-10-14
申请人： Jason Guo , Fai Ching
发明人： Jason Guo , Fai Ching
IPC分类号： G11C16/12 , G11C11/34
CPC分类号： G11C16/12
摘要： In a non-volatile memory, a programming cycle consists of the following phases: high voltage charging up, programming pulse, and discharge. The actual programming process only takes place in the programming pulse phase. Several break points are defined relative to elapsed time and introduced in the programming pulse phase. Upon receiving a suspend request, the programming operation will advance to the next break point, then discharge the high programming voltage and go to a suspend state. A separate counter is used to monitor the break points so that elapsed non-programming time can be deducted from the total programming pulse time when the programming operation is resumed. By doing so, the device can handle frequent suspend and resume requests. Since the total time duration in the programming pulse phase is equal for the programming operation with and without suspend and resume requests, the programming proceeds efficiently to completion.
摘要翻译：在非易失性存储器中，编程周期由以下阶段组成：高电压充电，编程脉冲和放电。实际的编程过程只发生在编程脉冲阶段。定义相对于经过时间的几个断点，并在编程脉冲阶段引入。在接收到暂停请求时，编程操作将进入下一个断点，然后释放高编程电压并进入挂起状态。使用单独的计数器来监视断点，以便在编程操作恢复时可以从总编程脉冲时间中扣除经过的非编程时间。通过这样做，设备可以处理频繁的挂起和恢复请求。由于编程脉冲阶段的总持续时间对于具有和不具有暂停和恢复请求的编程操作是相等的，所以编程有效地进行到完成。

10. 发明授权

US08169832B2 Methods of erase verification for a flash memory device 有权
标题翻译：闪存设备的擦除验证方法
公开(公告)号：US08169832B2
公开(公告)日：2012-05-01
申请号：US12909414
申请日：2010-10-21
申请人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
发明人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
IPC分类号： G11C11/34
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/3445
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
摘要翻译：公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

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