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1. 发明申请

US20080311744A1 MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SiCOH DIELECTRICS 有权
标题翻译：用于SiCOH电介质的无损伤双面加工的多层HARDMASK方案
公开(公告)号：US20080311744A1
公开(公告)日：2008-12-18
申请号：US12198602
申请日：2008-08-26
申请人： Nicholas C.M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
发明人： Nicholas C.M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
IPC分类号： H01L21/768
CPC分类号： H01L21/0331 , H01L21/76811 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/12576 , Y10T428/12611 , Y10T428/31667 , H01L2924/00
摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.
摘要翻译：具有用于90nm以上的有机硅酸盐玻璃基材料的互连结构，其中描述了使用线路优先方法的多层硬掩模的BEOL技术。本发明的互连结构实现了相应的改进的器件/互连性能，并且由于不暴露OSG材料以抵抗去除等离子体以及由于交替的无机/有机多层硬掩模堆叠而提供了实质的双镶嵌工艺窗口。后一特征意味着对于在特定蚀刻步骤期间被蚀刻的每个无机层，该领域中相应的图案转移层是有机的，反之亦然。

2. 发明授权

US07811926B2 Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics 有权
标题翻译：多层硬掩模方案，用于SiCOH电介质的无损双重镶嵌加工
公开(公告)号：US07811926B2
公开(公告)日：2010-10-12
申请号：US12198602
申请日：2008-08-26
申请人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
发明人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
IPC分类号： H01L21/00
CPC分类号： H01L21/0331 , H01L21/76811 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/12576 , Y10T428/12611 , Y10T428/31667 , H01L2924/00
摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.
摘要翻译：具有用于90nm以上的有机硅酸盐玻璃基材料的互连结构，其中描述了使用线路优先方法的多层硬掩模的BEOL技术。本发明的互连结构实现了相应的改进的器件/互连性能，并且由于不暴露OSG材料以抵抗去除等离子体以及由于交替的无机/有机多层硬掩模堆叠而提供了实质的双镶嵌工艺窗口。后一特征意味着对于在特定蚀刻步骤期间被蚀刻的每个无机层，该领域中相应的图案转移层是有机的，反之亦然。

3. 发明授权

US07371461B2 Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics 有权
公开(公告)号：US07371461B2
公开(公告)日：2008-05-13
申请号：US11034480
申请日：2005-01-13
申请人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
发明人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
IPC分类号： B32B9/04 , B32B27/00 , H01L21/31 , H01L21/312 , H01L21/314
CPC分类号： H01L21/0331 , H01L21/76811 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/12576 , Y10T428/12611 , Y10T428/31667 , H01L2924/00
摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

4. 发明授权

US08097932B2 Ultra low κ plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality 有权
标题翻译：超低＆kgr 使用含有SiCOH基质官能团和有机致孔剂功能的单一双功能前体的等离子体增强化学气相沉积方法
公开(公告)号：US08097932B2
公开(公告)日：2012-01-17
申请号：US12371180
申请日：2009-02-13
申请人： Son Van Nguyen , Stephen McConnell Gates , Deborah A. Neumayer , Alfred Grill
发明人： Son Van Nguyen , Stephen McConnell Gates , Deborah A. Neumayer , Alfred Grill
IPC分类号： H01L23/58
CPC分类号： C23C16/401 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02337 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/3122 , H01L21/31633 , H01L21/31695 , Y10T428/249921
摘要： A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having the molecular formula R4R5R6—Si—O—Si—R7R8R9, and trisiloxane derivatives having the molecular formula R10R11R12—Si—O—Si—R13R14—O—Si—R15R16R17 where R and R1-17 may or may not be identical and are selected from H, alkyl, alkoxy, epoxy, phenyl, vinyl, allyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. In addition to the method, the present application also provides SiCOH dielectrics made from the inventive method as well as electronic structures that contain the same.
摘要翻译：提供了由具有内置有机致孔剂的单一有机硅前体制备包含Si，C，O和H原子的SiCOH电介质材料的方法。具有内置有机致孔剂的单一有机硅前体选自具有分子式SiRR1R2R3的硅烷（SiH4）衍生物，具有分子式为R4R5R6-Si-O-Si-R7R8R9的二硅氧烷衍生物和分子式为R10R11R12- Si-O-Si-R13R14-O-Si-R15R16R17其中R和R1-17可以相同也可以不相同，并且可以选自H，烷基，烷氧基，环氧基，苯基，乙烯基，烯丙基，烯基或炔基，直链，支链，环状，多环，并且可以被含氧，含氮或氟的取代基官能化。除了该方法之外，本申请还提供了由本发明方法制备的SiCOH电介质以及含有该SiCOH的电子结构。

5. 发明申请

US20090304951A1 ULTRALOW DIELECTRIC CONSTANT LAYER WITH CONTROLLED BIAXIAL STRESS 审中-公开
标题翻译：超导介质恒定层与受控双向应力
公开(公告)号：US20090304951A1
公开(公告)日：2009-12-10
申请号：US12542287
申请日：2009-08-17
申请人： Christos Dimitrios Dimitrakopoulos , Stephen McConnell Gates , Alfred Grill , Michael Wayne Lane , Eric Gerhard Liniger , Xiao Hu Liu , Son Van Nguyen , Deborah Ann Neumayer , Thomas McCarroll Shaw
发明人： Christos Dimitrios Dimitrakopoulos , Stephen McConnell Gates , Alfred Grill , Michael Wayne Lane , Eric Gerhard Liniger , Xiao Hu Liu , Son Van Nguyen , Deborah Ann Neumayer , Thomas McCarroll Shaw
IPC分类号： C23C16/513 , G21G5/00
CPC分类号： H01L21/76834 , C23C16/30 , C23C16/56 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02348 , H01L21/3105 , H01L21/31058 , H01L21/31633 , H01L21/76801 , H01L21/76825 , H01L21/76828 , H01L21/76829 , H01L21/76832 , Y10T428/249953 , Y10T428/249969 , Y10T428/249979
摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.
摘要翻译：描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜的氧和水各自小于10ppm。还通过使用介电常数不超过2.8的方法描述材料。本发明克服了低双轴应力低于46MPa的薄膜形成问题。

6. 发明授权

US07357977B2 Ultralow dielectric constant layer with controlled biaxial stress 有权
标题翻译：具有受控双轴应力的超低介电常数层
公开(公告)号：US07357977B2
公开(公告)日：2008-04-15
申请号：US11034479
申请日：2005-01-13
申请人： Christos Dimitrios Dimitrakopoulos , Stephen McConnell Gates , Alfred Grill , Michael Wayne Lane , Eric Gerhard Liniger , Xiao Hu Liu , Son Van Nguyen , Deborah Ann Neumayer , Thomas McCarroll Shaw
发明人： Christos Dimitrios Dimitrakopoulos , Stephen McConnell Gates , Alfred Grill , Michael Wayne Lane , Eric Gerhard Liniger , Xiao Hu Liu , Son Van Nguyen , Deborah Ann Neumayer , Thomas McCarroll Shaw
IPC分类号： H01L23/52 , H01L23/58
CPC分类号： H01L21/76834 , C23C16/30 , C23C16/56 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02348 , H01L21/3105 , H01L21/31058 , H01L21/31633 , H01L21/76801 , H01L21/76825 , H01L21/76828 , H01L21/76829 , H01L21/76832 , Y10T428/249953 , Y10T428/249969 , Y10T428/249979
摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.
摘要翻译：描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜的氧和水各自小于10ppm。还通过使用介电常数不大于2.8的方法描述材料。本发明克服了低双轴应力低于46MPa的薄膜形成问题。

7. 发明授权

US06710450B2 Interconnect structure with precise conductor resistance and method to form same 有权
标题翻译：具有精确导体电阻的互连结构和形成相同的方法
公开(公告)号：US06710450B2
公开(公告)日：2004-03-23
申请号：US09795430
申请日：2001-02-28
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L23532
CPC分类号： H01L21/76835 , H01L21/02118 , H01L21/02126 , H01L21/02134 , H01L21/02137 , H01L21/022 , H01L21/02203 , H01L21/02282 , H01L21/3122 , H01L21/76811 , H01L21/7684
摘要： An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop layer has a second composition which is different from the first composition and the buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics. The interconnect structure further includes a polish stop layer formed on the patterned multilayer of spun-on dielectrics; and metal conductive regions formed within the patterned multilayer of spun-on dielectrics. Covalent bonding is achieved by employing an organosilane having functional groups that are capable of bonding with the top and bottom dielectric layers.
摘要翻译：提供了包括旋涂电介质的图案化多层的互连结构及其制造方法。互连结构包括形成在衬底的表面上的旋涂电介质的图案化多层。旋涂电介质的图案化多层由底部低k电介质，掩埋蚀刻停止层和顶部低k电介质组成，其中底部和顶部低k电介质具有第一组成，所述掩埋蚀刻停止层具有与第一组成不同的第二组成，并且掩埋蚀刻停止层共价键合到所述顶部和底部低k电介质。互连结构还包括形成在旋涂电介质的图案化多层上的抛光停止层; 以及形成在旋涂电介质的图案化多层中的金属导电区域。通过使用具有能够与顶部和底部电介质层结合的官能团的有机硅烷来实现共价键合。

8. 发明授权

US06603204B2 Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics 失效
公开(公告)号：US06603204B2
公开(公告)日：2003-08-05
申请号：US09795431
申请日：2001-02-28
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L2348
CPC分类号： H01L21/76835 , H01L21/76811 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

9. 发明授权

US06285050B1 Decoupling capacitor structure distributed above an integrated circuit and method for making same 失效
标题翻译：去耦电容器结构分布在集成电路上方和制造方法
公开(公告)号：US06285050B1
公开(公告)日：2001-09-04
申请号：US08998084
申请日：1997-12-24
申请人： Philip George Emma , Wei Hwang , Stephen McConnell Gates
发明人： Philip George Emma , Wei Hwang , Stephen McConnell Gates
IPC分类号： H01L27108
CPC分类号： H01L28/55 , H01L27/0688 , H01L27/10894
摘要： The present invention describes the use of large thin film (TF) capacitors having capacitance C made in a separate set of TF layers ABOVE the Si and wiring levels of an integrated circuit (IC). This C is very large. This invention describes a two-level IC architecture in which a metal/insulator/metal (MIM) capacitor structure comprises the upper level, and CMOS logic and memory circuits made in the Si wafer substrate comprise the lower level. The added thin film capacitance serves to stabilize the power supply voltage at a constant level during GHz IC operation.
摘要翻译：本发明描述了在集成电路（IC）的Si和布线电平之上使用具有在单独的一组TF层中制造的电容C的大型薄膜（TF）电容器。这C很大。本发明描述了一种二级IC架构，其中金属/绝缘体/金属（MIM）电容器结构包括上层，并且在Si晶片衬底中制成的CMOS逻辑和存储电路包括较低层。添加的薄膜电容用于在GHz IC操作期间将电源电压稳定在恒定水平。

10. 发明授权

US06756324B1 Low temperature processes for making electronic device structures 失效
标题翻译：制造电子器件结构的低温工艺
公开(公告)号：US06756324B1
公开(公告)日：2004-06-29
申请号：US08823843
申请日：1997-03-25
申请人： Stephen McConnell Gates
发明人： Stephen McConnell Gates
IPC分类号： H01L2131
CPC分类号： H01L29/458 , H01L21/3185 , H01L29/4908 , H01L29/78603 , H01L29/78669
摘要： A thin film transistor is described incorporating a gate electrode, a gate insulating layer, a semiconducting channel layer deposited on top of the gate insulating layer, an insulating encapsulation layer positioned on the channel layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer, all of which are situated on a plastic substrate. By enabling the use of plastics having low glass transition temperatures as substrates, the thin film transistors may be used in large area electronics such as information displays and light sensitive arrays for imaging which are flexible, lighter in weight and more impact resistant than displays fabricated on traditional glass substrates. The thin film transistors are useful in active matrix liquid crystal displays where the plastic substrates are transparent in the visible spectrum. Enablement of the use of such plastics is by way of the use of polymeric encapsulation films to coat the surfaces of the plastic substrates prior to subsequent processing and the use of novel low temperature processes for the deposition of thin film transistor structures.
摘要翻译：描述了一种薄膜晶体管，其结合了栅极电极，栅极绝缘层，沉积在栅极绝缘层顶部的半导体沟道层，位于沟道层上的绝缘封装层，源极，漏极和接触层在每个源极和漏极电极下方并且与至少沟道层接触，所有这些都位于塑料衬底上。通过使用具有低玻璃化转变温度的塑料作为基板，薄膜晶体管可以用于大面积电子设备中，例如用于成像的信息显示器和光敏阵列，其具有柔性，重量更轻，并且抗冲击性比制造在传统玻璃基板。薄膜晶体管可用于有源矩阵液晶显示器，其中塑料基板在可见光谱中是透明的。使用这种塑料是通过使用聚合物封装膜在随后的处理之前涂覆塑料基板的表面，以及使用用于沉积薄膜晶体管结构的新颖的低温工艺。

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