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1. 发明申请

US20050277066A1 Selective etch process for step and flash imprint lithography 审中-公开
标题翻译：用于步进和闪光压印光刻的选择性蚀刻工艺
公开(公告)号：US20050277066A1
公开(公告)日：2005-12-15
申请号：US10866563
申请日：2004-06-10
申请人： Ngoc Le , William Dauksher , Doug Resnick
发明人： Ngoc Le , William Dauksher , Doug Resnick
IPC分类号： G03F7/00 , G03F7/36 , G03F7/40 , H01L21/033
CPC分类号： G03F7/405 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/0337
摘要： A selective etch process for step and flash imprint lithography includes providing (30) a substrate (10); forming (32) a transfer layer (12) on the substrate; forming (34) an etch barrier layer (14) on the transfer layer; patterning (36) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the transfer layer; performing (38) an etch to substantially remove the residual layer; and performing (40) an etch with a mixture of nitrogen and hydrogen, and more preferably NH3, to substantially remove the portion of the transfer layer not underlying the etch barrier layer.
摘要翻译：用于步进和快速压印光刻的选择性蚀刻工艺包括提供（30）衬底（10）; 在所述基板上形成（32）转印层（12）; 在所述转移层上形成（34）蚀刻阻挡层（14）; 在通过模板的紫外线固化的同时用模板（16）对蚀刻阻挡层进行图案化（36），从而在转印层上产生图案化的蚀刻阻挡层和残留层（20）; 执行（38）蚀刻以基本上去除残余层; 并且用氮和氢的混合物，更优选地NH 3 3进行（40）蚀刻，以基本上去除不在蚀刻阻挡层下方的转移层的部分。

2. 发明申请

US20060115979A1 Plasma etch process for multilayer vias having an organic layer with vertical sidewalls 失效
公开(公告)号：US20060115979A1
公开(公告)日：2006-06-01
申请号：US11000832
申请日：2004-11-30
申请人： Donald Weston , William Dauksher , Ngoc Le
发明人： Donald Weston , William Dauksher , Ngoc Le
IPC分类号： H01L21/4763 , H01L21/461
CPC分类号： H01L21/76802 , H01L21/76838 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer 14 and etching through the dielectric layer 14 and the organic bonding material 32 with 60CF4/20Ar/60CHF3/20N2. The resist may then be removed with an anisotropic high density oxygen plasma.

3. 发明申请

US20060110914A1 Direct imprinting of etch barriers using step and flash imprint lithography 失效
标题翻译：使用步骤和闪光压印光刻技术直接刻印蚀刻阻挡层
公开(公告)号：US20060110914A1
公开(公告)日：2006-05-25
申请号：US10995800
申请日：2004-11-22
申请人： Kathy Gehoski , William Dauksher , Ngoc Le , Douglas Resnick
发明人： Kathy Gehoski , William Dauksher , Ngoc Le , Douglas Resnick
IPC分类号： H01L21/4763
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/76814 , H01L21/76838
摘要： A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the substrate; and performing (48) an etch to substantially remove the residual layer. Optionally, a patterning layer (52) may be formed on the substrate (12) prior to forming the etch barrier layer (14). Additionally, an adhesive layer (13) may be applied (42) between the substrate (12) and the etch barrier layer (14).
摘要翻译：步进和闪光印记光刻技术的直接印刷工艺包括提供（40）基材（12）; 在衬底上形成（44）蚀刻阻挡层（14）; 在通过模板的紫外线固化的同时用模板（16）对蚀刻阻挡层进行图案化（46），从而在衬底上产生图案化的蚀刻阻挡层和残余层（20）; 并执行（48）蚀刻以基本上去除残留层。可选地，在形成蚀刻阻挡层（14）之前，可以在衬底（12）上形成图案化层（52）。另外，可以在衬底（12）和蚀刻阻挡层（14）之间施加粘合剂层（13）（42）。

4. 发明授权

US5476818A Semiconductor structure and method of manufacture 失效
标题翻译：半导体结构及制造方法
公开(公告)号：US5476818A
公开(公告)日：1995-12-19
申请号：US293350
申请日：1994-08-19
申请人： Arnold W. Yanof , William Dauksher
发明人： Arnold W. Yanof , William Dauksher
IPC分类号： H01L21/60 , H01L23/055 , H01L23/32 , H01L23/49
CPC分类号： H01L24/10 , H01L23/055 , H01L23/32 , H01L24/13 , H01L24/81 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/81801 , H01L2924/01004 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15184 , H01L2924/16152 , H01L2924/16195 , H01L2924/30105 , H01L2924/30107 , Y10T29/4913 , Y10T29/49146
摘要： A semiconductor structure (8) comprising a semiconductor chip support structure (9), a circuit board substrate (40) with circuit board substrate probes (36) extending therefrom and a method for fabricating the semiconductor structure (8). The semiconductor chip support structure (9) includes, for example, clips (43, 53) to replaceably mount semiconductor chips (47, 48) to the semiconductor chip support structure (9). The circuit board substrate (40) is mated with the semiconductor chip support structure (9) so that the circuit board substrate probes (36) contact bonding pads (49) on the semiconductor chips (47, 48). If a semiconductor chip (47, 48) becomes damaged, the circuit board substrate (40) may be separated from the semiconductor chip support structure (9) and the damaged semiconductor chip (47, 48) replaced with a good semiconductor chip (47, 48).
摘要翻译：一种半导体结构（8），包括半导体芯片支撑结构（9），具有从其延伸的电路板衬底探针（36）的电路板衬底（40）和用于制造半导体结构（8）的方法。半导体芯片支撑结构（9）包括例如用于将半导体芯片（47,48）可替换地安装到半导体芯片支撑结构（9）的夹子（43,43）。电路板基板（40）与半导体芯片支撑结构（9）配合，使得电路板基板探针（36）接触半导体芯片（47,48）上的接合焊盘（49）。如果半导体芯片（47,48）被损坏，则可以将电路板基板（40）与半导体芯片支撑结构（9）分离，并且将损坏的半导体芯片（47,48）替换为良好的半导体芯片（47,48） 48）。

5. 发明申请

US20070048625A1 Lithographic template and method of formation and use 失效
标题翻译：光刻模板及其形成和使用方法
公开(公告)号：US20070048625A1
公开(公告)日：2007-03-01
申请号：US11213071
申请日：2005-08-26
申请人： Kevin Nordquist , Jeffrey Baker , William Dauksher
发明人： Kevin Nordquist , Jeffrey Baker , William Dauksher
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F7/0017 , B82Y10/00 , B82Y40/00 , G03F7/0002
摘要： A lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template is provided. The lithographic template (10) and the method of making comprises forming a transparent conductive layer (16) over a substrate (12). A SiCN layer (18) is formed over the transparent conductive layer (16), and a patterning layer (20) formed on the SiCN layer (18). The SiCN layer (18) is converted to an SiO2 layer by applying an O2 plasma (23). The SiO2 layer prevents damage to the transparent conductive layer (16) during cleaning and provides a binding mechanism for the imprint release coating.
摘要翻译：提供了光刻模板，形成光刻模板的方法以及用该光刻模板形成器件的方法。光刻模板（10）和制造方法包括在衬底（12）上形成透明导电层（16）。在透明导电层（16）上形成SiCN层（18），形成在SiCN层（18）上的图形层（20）。通过施加O 2等离子体（23）将SiCN层（18）转化为SiO 2层。 SiO 2层防止在清洁期间对透明导电层（16）的损坏，并提供用于压印剥离涂层的结合机构。

6. 发明申请

US20090035939A1 FABRICATION METHOD TO MINIMIZE BALLAST LAYER DEFECTS 审中-公开
标题翻译：最小化BALLAST层缺陷的制造方法
公开(公告)号：US20090035939A1
公开(公告)日：2009-02-05
申请号：US11830985
申请日：2007-07-31
申请人： Steven Young , William Dauksher , Emmett Howard , Donald Weston
发明人： Steven Young , William Dauksher , Emmett Howard , Donald Weston
IPC分类号： H01L21/44
CPC分类号： H01J9/025 , H01J1/304 , H01J2201/3195
摘要： A method for minimizing fabrication defects in ballast contact to a conductor in monolithically integrated semiconductor devices includes forming a sloping sidewall (318, 424) in both an insulating layer (106, 718) overlying a conductive layer (104, 714) by etching with a an RF biased fluorine based chemistry and an RF biased chlorine based chemistry, respectively, as defined by a single resist layer (108) having a sloped sidewall (212). A ballast layer (526, 726) is deposited on the structure (100, 700) and metal contacts (632, 634, 636, 638, 722) are disposed on the ballast layer (526, 722).
摘要翻译：一种用于使在单片集成半导体器件中的导体的镇流器接触中的制造缺陷最小化的方法包括：在覆盖导电层（104,714）的绝缘层（106,78）中形成倾斜侧壁（318,424）分别由具有倾斜侧壁（212）的单个抗蚀剂层（108）限定的RF偏置氟基化学和RF偏置氯基化学。沉积在结构（100,700）上的压载层（526,726），并且金属触点（632,634,636,638,722）设置在镇流器层（526,722）上。

7. 发明申请

US20060222968A1 LITHOGRAPHIC TEMPLATE AND METHOD OF FORMATION AND USE 有权
标题翻译： LITHOGRAPHIC模板及其形成与使用方法
公开(公告)号：US20060222968A1
公开(公告)日：2006-10-05
申请号：US11423621
申请日：2006-06-12
申请人： Albert Talin , Jeffrey Baker , William Dauksher , Andy Hooper , Douglas Resnick
发明人： Albert Talin , Jeffrey Baker , William Dauksher , Andy Hooper , Douglas Resnick
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： B82Y10/00 , B82Y40/00 , C23C14/086 , G03F7/0002 , G03F7/0017 , G03F7/093
摘要： This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, photonic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), a transparent conductive layer (16) formed on a surface (14) of the substrate (12) by low pressure sputtering to a thickness that allows for preferably 90% transmission of ultraviolet light therethrough, and a patterning layer (20) formed on a surface (18) of the transparent conductive layer (16). The template (10) is used in the fabrication of a semiconductor device (30) for affecting a pattern in device (30) by positioning the template (10) in close proximity to semiconductor device (30) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template. Radiation is then applied through the template so as to cure portions of the radiation sensitive material and define the pattern in the radiation sensitive material. The template (10) is then removed to complete fabrication of semiconductor device (30).
摘要翻译：本发明涉及半导体器件，微电子器件，微电子机械器件，微流体器件，光子器件，更具体地涉及光刻模板，形成光刻模板的方法和用光刻模板形成器件的方法。光刻模板（10）形成为具有基板（12），通过低压溅射形成在基板（12）的表面（14）上的透明导电层（16）至允许优选90％透射率的厚度紫外光，以及形成在透明导电层（16）的表面（18）上的图形层（20）。模板（10）用于通过将模板（10）定位成紧邻其上形成有辐射敏感材料的半导体器件（30）而影响器件（30）中的图案的半导体器件（30）的制造，以及施加压力以使辐射敏感材料流入存在于模板上的浮雕图像。然后通过模板施加辐射，以便固化辐射敏感材料的部分并限定辐射敏感材料中的图案。然后移除模板（10）以完成半导体器件（30）的制造。

8. 发明授权

US5513430A Method for manufacturing a probe 失效
标题翻译：探针制造方法
公开(公告)号：US5513430A
公开(公告)日：1996-05-07
申请号：US293365
申请日：1994-08-19
申请人： Arnold W. Yanof , William Dauksher
发明人： Arnold W. Yanof , William Dauksher
IPC分类号： G01R3/00 , H05K3/40 , H05K3/02
CPC分类号： H05K3/4007 , G01R3/00 , H05K2201/0347 , H05K2201/0367 , H05K2201/09836 , H05K2201/09845 , H05K2203/0542 , H05K2203/0577 , Y10T29/49155
摘要： A probe card (40, 55) having probe card probes (36, 56) and a method for fabricating the probe card probes (36, 56). A layer of resist (23) is formed on a plating base (21). The layer of resist (23) is exposed to radiation (32) and developed to provide angled, tapered openings (33) exposing portions of the plating base (22). An electrically conductive material is electroplated on the exposed portions of the plating base (22) and fills the angled, tapered openings (33). The layer of resist (23) and portions of the plating base (22) between the electroplated conductive material are removed. The electrically conductive material forms the probe card probes (36) which are angled and tapered. In addition, the compliant probe card probes (56) may be stair-step shaped.
摘要翻译：具有探针卡探针（36,56）的探针卡（40,55）和用于制造探针卡探针（36,56）的方法。在电镀基体（21）上形成有抗蚀剂层（23）。抗蚀剂层（23）暴露于辐射（32）并显影以提供倾斜的锥形开口（33），暴露电镀基底（22）的部分。导电材料电镀在电镀基座（22）的露出部分上并填充有角度的锥形开口（33）。去除了电镀层（23）和电镀基底（22）在电镀导电材料之间的部分。导电材料形成了成角度和锥形的探针卡探头（36）。此外，兼容的探针卡探针（56）可以是台阶形状。

9. 发明申请

US20070099336A1 Plasma etch process for defining catalyst pads on nanoemissive displays 失效
标题翻译：用于在纳米显示器上定义催化剂垫的等离子体蚀刻工艺
公开(公告)号：US20070099336A1
公开(公告)日：2007-05-03
申请号：US11263793
申请日：2005-10-31
申请人： Donald Weston , William Dauksher , Emmett Howard
发明人： Donald Weston , William Dauksher , Emmett Howard
IPC分类号： H01L51/40
CPC分类号： H01J9/025 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , H01J2201/30469 , Y10S977/742
摘要： A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing the photoresist with an ash process; and removing the veils and preparing the surface for carbon nanotube growth with a semi-aqueous hydroxylamine solution.
摘要翻译：一种用于形成用于碳纳米管生长的催化剂层的方法，包括在阴极金属层或镇流电阻层之一上形成具有第一和第二部分的催化剂层; 在第一部分上图案化光致抗蚀剂; 用氯/氩等离子体蚀刻第二部分; 用灰过程去除光致抗蚀剂; 并用半水羟胺溶液除去面纱并制备用于碳纳米管生长的表面。

10. 发明申请

US20060003551A1 Ultra-thin die and method of fabricating same 有权
公开(公告)号：US20060003551A1
公开(公告)日：2006-01-05
申请号：US10881144
申请日：2004-06-30
申请人： David Mancini , Young Chung , William Dauksher , Donald Weston , Steven Young , Robert Baird
发明人： David Mancini , Young Chung , William Dauksher , Donald Weston , Steven Young , Robert Baird
IPC分类号： H01L21/301 , H01L21/46
CPC分类号： H01L21/3065 , H01L21/78 , Y10S438/977
摘要： In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

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