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1. 发明授权

US5860016A Arrangement, system, and method for automatic remapping of frame buffers when switching operating modes 失效
标题翻译：切换操作模式时自动重新映射帧缓冲区的布置，系统和方法
公开(公告)号：US5860016A
公开(公告)日：1999-01-12
申请号：US720392
申请日：1996-09-30
申请人： Narasimha R. Nookala , Otto Sponring , Kameswaran Sivamani
发明人： Narasimha R. Nookala , Otto Sponring , Kameswaran Sivamani
IPC分类号： G09G3/20 , G09G3/36 , G06F1/32
CPC分类号： G09G3/3611 , G09G2330/022 , G09G2340/0428 , G09G3/20
摘要： An arrangement, system, and method to allow a computer system to have a normal operating mode with full display capability and a low-power operating mode with reduced display capability is provided. The computer system automatically switches to the low-power operating mode from the normal operating mode following a programmable period of inactivity. While display data is retrieved from an external DRAM in the normal operating mode, display data is retrieved from an internal SRAM in the low-power operating mode. The computer system switches back to the normal operating mode when one of the predetermined activities is detected.
摘要翻译：提供了允许计算机系统具有全显示能力的正常操作模式和具有降低的显示能力的低功率操作模式的布置，系统和方法。计算机系统在可编程的不活动时间段后，从正常操作模式自动切换到低功耗工作模式。当在正常操作模式下从外部DRAM检索显示数据时，在低功率操作模式下从内部SRAM检索显示数据。当检测到预定活动之一时，计算机系统切换回正常操作模式。

2. 发明授权

US5923895A Method and arrangement to effectively retrieve residual data from a buffer 失效
标题翻译：有效地从缓冲器中检索残留数据的方法和装置
公开(公告)号：US5923895A
公开(公告)日：1999-07-13
申请号：US751188
申请日：1996-11-15
申请人： Narasimha R. Nookala , Otto Sponring , Kameswaran Sivamani
发明人： Narasimha R. Nookala , Otto Sponring , Kameswaran Sivamani
IPC分类号： G06F5/06 , G06F13/00 , G11C7/00
CPC分类号： G06F5/06
摘要： A mechanism to effectively retrieve residual data received from a serial data source is provided. As the shift register receives serial data from the serial data source, the activities and content of the shift register is monitored. Status bits are set to reflect the activities and content. These status bits are used to determine whether the shift register contains residual data and whether such residual data should be ignored the serial data received from the serial data source is output to a destination.
摘要翻译：提供了一种有效检索从串行数据源接收的残留数据的机制。当移位寄存器从串行数据源接收串行数据时，监视移位寄存器的活动和内容。设置状态位以反映活动和内容。这些状态位用于确定移位寄存器是否包含残差数据，并且是否应该忽略这样的残差数据，将从串行数据源接收的串行数据输出到目的地。

3. 发明授权

US5878257A Self-booting mechanism to allow dynamic system configuration and diagnostic 失效
标题翻译：自启动机制允许动态系统配置和诊断
公开(公告)号：US5878257A
公开(公告)日：1999-03-02
申请号：US749876
申请日：1996-11-15
申请人： Narasimha R. Nookala , Kameswaran Sivamani , Otto Sponring
发明人： Narasimha R. Nookala , Kameswaran Sivamani , Otto Sponring
IPC分类号： G06F9/06 , G06F9/44 , G06F9/445 , C06F9/06
CPC分类号： G06F9/4411
摘要： A mechanism to allow dynamic configurations and/or diagnostic of a computer system from a remote location is provided. The computer system receives instruction codes of a program from a data source. When executed by the CPU, the instruction codes performs the necessary erase and program operations to embed a firmware program onto to the flash memory. The firmware program can be used for configurations or diagnostic purpose.
摘要翻译：提供了允许来自远程位置的计算机系统的动态配置和/或诊断的机制。计算机系统从数据源接收程序的指令代码。当CPU执行时，指令代码执行必要的擦除和程序操作，以将固件程序嵌入闪存。固件程序可用于配置或诊断目的。

4. 发明授权

US5761465A System for coupling asynchronous data path to field check circuit of synchronous data path when the asynchronous data path communicating data in synchronous format 失效
标题翻译：异步数据路径以同步格式通信数据时，将异步数据路径耦合到同步数据路径的现场检查电路的系统
公开(公告)号：US5761465A
公开(公告)日：1998-06-02
申请号：US625661
申请日：1996-03-29
申请人： Hanumanthrao V. Nimishakvi , Kameswaran Sivamani
发明人： Hanumanthrao V. Nimishakvi , Kameswaran Sivamani
IPC分类号： H04L1/00 , H04L12/56 , H04L25/49 , H04L29/06 , H04L29/08 , G06F11/00
CPC分类号： H04L1/0057 , H04L25/49 , H04L29/06 , H04L69/18 , H04L69/324
摘要： A data communication circuit of a computer system, includes transmitter and receiver circuits each having first and second data paths for respectively communicating synchronously and asynchronously formatted data on an alternatively selected basis, and a control circuit for controlling such communications. Included in the first data paths of the transmitter and receiver circuits are certain field check generating or error checking circuitry which are switchably coupled by their respective control circuits to their corresponding second data paths when synchronously formatted data is being asynchronously communicated through the second data paths.
摘要翻译：计算机系统的数据通信电路包括各自具有第一和第二数据路径的发射机和接收机电路，用于分别在可选择的基础上传送同步和异步格式化的数据，以及用于控制这种通信的控制电路。包括在发射机和接收机电路的第一数据路径中的是一些现场校验生成或错误校验电路，当同步格式化数据通过第二数据路径进行异步传送时，它们可被其各自的控制电路切换耦合到其对应的第二数据路径。

5. 发明授权

US5276888A Computer system with interrupts transparent to its operating system and application programs 失效
标题翻译：具有中断的计算机系统对其操作系统和应用程序是透明的
公开(公告)号：US5276888A
公开(公告)日：1994-01-04
申请号：US964788
申请日：1992-10-22
申请人： James Kardach , Gregory Mathews , Cau Nguyen , Sung S. Cho , Kameswaran Sivamani , David Vannier , Shing Wong , Edward Zager
发明人： James Kardach , Gregory Mathews , Cau Nguyen , Sung S. Cho , Kameswaran Sivamani , David Vannier , Shing Wong , Edward Zager
IPC分类号： G06F9/48 , G06F11/14 , G06F9/46 , G06F12/00
CPC分类号： G06F9/4812
摘要： A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.
摘要翻译：通过在微处理器CPU芯片的外部引脚处的电信号的断言来调用透明系统中断。一旦断言这个中断，CPU就会在专用的RAM区域开始程序的执行，这个操作系统和所有应用程序无法访问。一组指令，可能是安装了CPU芯片的系统所特有的，可以为中断提供服务。通常，中断服务程序之前立即断定中断的CPU和相关组件的状态将被保存到专用的RAM区域。从中断恢复是在识别到调用RESUME指令的外部事件时完成的，该指令使CPU和相关组件恢复到与中断之前存在的完全相同的状态，并且以对该时间执行的任何程序完全透明的方式的中断。

6. 发明授权

US5274826A Transparent system interrupts with automated input/output trap restart 失效
标题翻译：透明系统中断，自动输入/输出陷阱重启
公开(公告)号：US5274826A
公开(公告)日：1993-12-28
申请号：US53960
申请日：1993-04-26
申请人： James Kardach , Cau Nguyen , Kameswaran Sivamani
发明人： James Kardach , Cau Nguyen , Kameswaran Sivamani
IPC分类号： G06F9/46 , G06F9/48 , G06F12/14 , G06F13/24
CPC分类号： G06F9/4812 , G06F9/463
摘要： A CPU of a microprocessor system is modified to post an executed write I/O instruction upon completion of writing by the bus unit. A dedicated memory area is provided for storing a customizable system interrupt service routine, program state data at the time of interruption and an I/O trap indicator indicating the CPU was interrupted during execution of an I/O instruction. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted and continued execution including automatic re-execution of an interrupted I/O instruction. As a result, a system integrator or OEM may provide transparent system level interrupts with automated I/O trap restart that will operate reliably in any operating environment, and be relieved of the heavy burden of managing I/O trap restart.
摘要翻译：修改微处理器系统的CPU，以在总线单元完成写入时发布执行的写入I / O指令。提供专用存储器区域，用于存储可定制的系统中断服务程序，中断时的程序状态数据和指示CPU在执行I / O指令期间中断的I / O陷阱指示器。专用存储器区域通常不被映射为主存储器空间的一部分，从而使其不能被操作系统和应用程序访问。具有比所有其他可屏蔽和不可屏蔽中断更高优先级的不可屏蔽系统监控中断被添加到CPU中断。一个RESUME指令被添加到CPU指令，以便在CPU被中断之前恢复到该状态并继续执行，包括自动重新执行中断的I / O指令。因此，系统集成商或OEM可能会提供透明的系统级中断，并具有可在任何操作环境中可靠运行的自动I / O陷阱重新启动，并且可以减轻管理I / O陷阱重启的沉重负担。

7. 发明授权

US5809341A Circuit for transmitting received character when detection signal is not activated and transmitting substitute character when the detection signal is activated 失效
标题翻译：当检测信号未被激活时发送接收字符的电路，当检测信号被激活时发送替代字符
公开(公告)号：US5809341A
公开(公告)日：1998-09-15
申请号：US672641
申请日：1996-06-28
申请人： Hanumanthrao V. Nimishakvi , Kameswaran Sivamani
发明人： Hanumanthrao V. Nimishakvi , Kameswaran Sivamani
IPC分类号： H04L1/00 , H04L12/56 , H04L25/49 , H04L29/06 , H04L29/08 , G06F15/02
CPC分类号： H04L25/49 , H04L1/0057 , H04L29/06 , H04L69/18 , H04L69/324
摘要： A data communication circuit of a computer system, includes transmitter and receiver circuits each having first and second data paths for respectively communicating synchronously and asynchronously formatted data on an alternatively selected basis, and a control circuit for controlling such communications. Included in the first data paths of the transmitter and receiver circuits are certain field check generating or error checking circuitry which are switchably coupled by their respective control circuits to their corresponding second data paths when synchronously formatted data is being asynchronously communicated through the second data paths. Included in the second data paths of the transmitter and receiver circuits are certain mapping logic to respectively accomodate the transmission and reception of Async-HDLC formatted data with transparency mapping.
摘要翻译：计算机系统的数据通信电路包括各自具有第一和第二数据路径的发射机和接收机电路，用于分别在可选择的基础上传送同步和异步格式化的数据，以及用于控制这种通信的控制电路。包括在发射机和接收机电路的第一数据路径中的是一些现场校验生成或错误校验电路，当同步格式化数据通过第二数据路径进行异步传送时，它们可被其各自的控制电路切换耦合到其对应的第二数据路径。包含在发射机和接收机电路的第二数据路径中的是一些映射逻辑，以分别容纳具有透明度映射的Async-HDLC格式化数据的发送和接收。

8. 发明授权

US5175853A Transparent system interrupt 失效
标题翻译：透明系统中断
公开(公告)号：US5175853A
公开(公告)日：1992-12-29
申请号：US787762
申请日：1991-11-06
申请人： James Kardach , Gregory Mathews , Cau Nguyen , Sung S. Cho , Kameswaran Sivamani , David Vannier , Shing Wong , Edward Zager
发明人： James Kardach , Gregory Mathews , Cau Nguyen , Sung S. Cho , Kameswaran Sivamani , David Vannier , Shing Wong , Edward Zager
IPC分类号： G06F9/48 , G06F11/14
CPC分类号： G06F9/4812
摘要： A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.
摘要翻译：通过在微处理器CPU芯片的外部引脚处的电信号的断言来调用透明系统中断。一旦断言这个中断，CPU就会在专用的RAM区域开始程序的执行，这个操作系统和所有应用程序无法访问。一组指令，可能是安装了CPU芯片的系统所特有的，可以为中断提供服务。通常，中断服务程序之前立即断定中断的CPU和相关组件的状态将被保存到专用的RAM区域。从中断恢复是在识别到调用RESUME指令的外部事件时完成的，该指令使CPU和相关组件恢复到与中断之前存在的完全相同的状态，并且以对该时间执行的任何程序完全透明的方式的中断。

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