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1. 发明授权

US07159102B2 Branch control memory 失效
标题翻译：分支控制存储器
公开(公告)号：US07159102B2
公开(公告)日：2007-01-02
申请号：US10869760
申请日：2004-06-15
申请人： Naohiko Irie , Tony Lee Werner
发明人： Naohiko Irie , Tony Lee Werner
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/322 , G06F9/3806 , G06F9/3842 , G06F9/3846
摘要： A branch control memory store branch instructions which are adapted for optimizing performance of programs run on electronic processors. Flexible instruction parameter fields permit a variety of new branch control and branch instruction implementations best suited for a particular computing environment. These instructions also have separate prediction bits, which are used to optimize loading of target instruction buffers in advance of program execution, so that a pipeline within the processor achieves superior performance during actual program execution.
摘要翻译：分支控制存储器存储适于优化在电子处理器上运行的程序的性能的分支指令。灵活的指令参数字段允许最适合特定计算环境的各种新的分支控制和分支指令实现。这些指令还具有单独的预测位，其用于在程序执行之前优化目标指令缓冲器的加载，使得处理器内的流水线在实际程序执行期间实现优异的性能。

2. 发明授权

US06772325B1 Processor architecture and operation for exploiting improved branch control instruction 失效
标题翻译：处理器架构和操作，用于利用改进的分支控制指令
公开(公告)号：US06772325B1
公开(公告)日：2004-08-03
申请号：US09410682
申请日：1999-10-01
申请人： Naohiko Irie , Tony Lee Werner
发明人： Naohiko Irie , Tony Lee Werner
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/322 , G06F9/3806 , G06F9/3842 , G06F9/3846
摘要： A processor is disclosed utilizing improved branch control and branch instructions for optimizing performance of programs run on such processors. Flexible instruction parameter fields permit a variety of new branch control and branch instruction implementations best suited for a particular computing environment. These instructions also have separate prediction bits, which are used to optize loading of target instruction buffers in advance of program execution, so that a pipeline within the processor achieves superior performance during actual program execution.
摘要翻译：公开了利用改进的分支控制和分支指令来优化在这种处理器上运行的程序的性能的处理器。灵活的指令参数字段允许最适合特定计算环境的各种新的分支控制和分支指令实现。这些指令还具有单独的预测位，其用于在程序执行之前优化加载目标指令缓冲器，使得处理器内的流水线在实际程序执行期间实现优异的性能。

3. 发明授权

US06449712B1 Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions 失效
标题翻译：用较大的固定长度指令的序列来模拟执行较小的固定长度分支/延迟时隙指令
公开(公告)号：US06449712B1
公开(公告)日：2002-09-10
申请号：US09410851
申请日：1999-10-01
申请人： Naohiko Irie , Tony Lee Werner , Chih-Jui Peng , Sebastian H. Ziesler , Jackie A. Freeman , Sivaram Krishnan
发明人： Naohiko Irie , Tony Lee Werner , Chih-Jui Peng , Sebastian H. Ziesler , Jackie A. Freeman , Sivaram Krishnan
IPC分类号： G06F9455
CPC分类号： G06F9/30174 , G06F9/30058 , G06F9/3842
摘要： A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.
摘要翻译：构造为执行32位固定长度指令集体系结构的处理器元件向后兼容，用于通过将16位指令中的每一个转换为一个或多个32位的序列来执行16位固定长度指令集架构说明。 32位指令集架构包括“准备分支”指令，允许在分支之前设置分支指令的目标地址。组合32位准备到分支和分支指令以执行与16位延迟时隙指令相结合的16位分支指令。

4. 发明授权

US06374348B1 Prioritized pre-fetch/preload mechanism for loading and speculative preloading of candidate branch target instruction 有权
标题翻译：候选分支目标指令的加载和推测预加载的优先预取/预载机制
公开(公告)号：US06374348B1
公开(公告)日：2002-04-16
申请号：US09690340
申请日：2000-10-17
申请人： Naohiko Irie , Tony Lee Werner
发明人： Naohiko Irie , Tony Lee Werner
IPC分类号： G06F938
CPC分类号： G06F9/3804 , G06F9/30058 , G06F9/322 , G06F9/3842 , G06F9/3846 , G06F9/3885
摘要： An improved preload/prefetching architecture is disclosed for controlling branch target instruction loading in a pipelined processor. Branch target instructions can be speculatively preloaded/prefetched based on a first prediction indicator provided in a branch control instruction, and they also can be actually loaded/fetched based on a second prediction indicator provided in a branch instruction. This mechanism results in reduced cache latency during program execution. The preloading/prefetching of branch target instructions can also be prioritized under software control to optimize instruction execution, based on particular indicators specified for branch target instructions within a branch hint buffer.
摘要翻译：公开了改进的预加载/预取架构来控制流水线处理器中的分支目标指令加载。分支目标指令可以基于分支控制指令中提供的第一预测指示符来推测性预加载/预取，并且还可以基于分支指令中提供的第二预测指示符来实际加载/取出分支目标指令。这种机制导致程序执行期间的缓存延迟减少。分支目标指令的预加载/预取也可以在软件控制下进行优先级排序，以根据为分支提示缓冲区内的分支目标指令指定的特定指标优化指令执行。

5. 发明授权

US07493479B2 Method and apparatus for event detection for multiple instruction-set processor 有权
标题翻译：多指令集处理器的事件检测方法和装置
公开(公告)号：US07493479B2
公开(公告)日：2009-02-17
申请号：US10458289
申请日：2003-06-11
申请人： Masayuki Kabasawa , Naohiko Irie , Takahiro Irita , Tetsuya Yamada , Takanobu Tsunoda
发明人： Masayuki Kabasawa , Naohiko Irie , Takahiro Irita , Tetsuya Yamada , Takanobu Tsunoda
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00 , G06F7/38
CPC分类号： G06F9/30174 , G06F9/3851
摘要： A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.
摘要翻译：提供了一种用于多指令集处理器的事件检测的方法和装置。在该装置的一个示例中，数据处理装置包括被配置为执行第一指令集作为特定指令的指令执行装置; 指令转换电路，被配置为将第二指令集的指令转换为第一指令集的第一指令串，并且还被配置为将第一指令串提供给指令执行装置; 以及计数器装置，被配置为对规定的事件进行计数，其中所述指令转换电路还被配置为当所述计数器装置满足规定条件时输出规定的指令。

6. 发明授权

US07340078B2 Multi-sensing devices cooperative recognition system 失效
标题翻译：多感器设备协同识别系统
公开(公告)号：US07340078B2
公开(公告)日：2008-03-04
申请号：US10876596
申请日：2004-06-28
申请人： Hiroaki Shikano , Naohiko Irie
发明人： Hiroaki Shikano , Naohiko Irie
IPC分类号： G06K9/00
CPC分类号： G06K9/00664
摘要： Disclosed here is an information processing system capable of recognizing actions and circumstances of a user with respect to both space and time as a “situation” to recognize the user's request using a plurality of sensing nodes that work cooperatively with each another, thereby responding autonomously to the user's request according to the recognition results. The plurality of sensing nodes and a responding device are disposed in a target space to build up a network for recognizing the situation in the target space. And, a plurality of recognition means are used to recognize the situation with respect to both space and time related to the existence of the user. And, an integral processing portion (master) is selected from among the plurality of sensing nodes, thereby dispersing the system load. If there are a plurality of users, the system can make recognition in accordance with the request of each of those users.
摘要翻译：这里公开了一种信息处理系统，其能够将用户相对于空间和时间的动作和情况识别为使用多个彼此协作工作的感测节点来识别用户的请求的“情况”，从而自主地响应于用户的请求根据识别结果。多个感测节点和响应装置设置在目标空间中以构建用于识别目标空间中的情况的网络。并且，使用多个识别装置来识别与用户的存在相关的空间和时间的情况。并且，从多个感测节点中选择积分处理部（主），从而分散系统负载。如果存在多个用户，则系统可以根据每个用户的请求进行识别。

7. 发明申请

US20070284619A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070284619A1
公开(公告)日：2007-12-13
申请号：US11797034
申请日：2007-04-30
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： H01L29/73
CPC分类号： G01R31/318572 , G11C5/063 , G11C11/417 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2924/0002 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H01L2924/00
摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.
摘要翻译：在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

8. 发明申请

US20060146635A1 Semiconductor device 有权
公开(公告)号：US20060146635A1
公开(公告)日：2006-07-06
申请号：US11363060
申请日：2006-02-28
申请人： Takao Watanabe , Kunio Uchiyama , Osamu Nishii , Naohiko Irie , Hiroyuki Mizuno
发明人： Takao Watanabe , Kunio Uchiyama , Osamu Nishii , Naohiko Irie , Hiroyuki Mizuno
IPC分类号： G11C5/14
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/147 , G11C11/417 , Y02D10/171
摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

9. 发明申请

US20050027965A1 Information processing device 失效
标题翻译：信息处理装置
公开(公告)号：US20050027965A1
公开(公告)日：2005-02-03
申请号：US10883758
申请日：2004-07-06
申请人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
发明人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
IPC分类号： G06F9/38 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/45 , G06F15/00
CPC分类号： G06F9/30174 , G06F9/30014 , G06F9/3861 , G06F9/3877 , G06F9/3879
摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when 4corresponding data is detected in a data checking part.
摘要翻译：硬件加速器用于在信息处理设备中执行浮点字节码。对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。为了实现这一点，由硬件加速器监视从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到4个对应数据时，向CPU发送取消请求以禁止执行FPU操作部分。

10. 发明授权

US08122233B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US08122233B2
公开(公告)日：2012-02-21
申请号：US12124232
申请日：2008-05-21
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.
摘要翻译：一种信息处理装置，包括：处理单元; 外围电路模块; 以及引导地址寄存器，其中所述信息处理设备包括具有低于所述第一操作模式的操作电流的第一操作模式和第二操作模式，其中所述引导地址寄存器保存要执行的指令的地址所述处理单元首先当所述引导地址寄存器从所述第二操作模式返回到所述第一操作模式时，其中当所述信息处理设备从所述第二操作模式转换到所述第一操作时，所述地址从所述引导地址输出到所述处理单元模式。

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