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1. 发明专利

JP2007058875A Programmable branch prediction system and method for computer system 审中-公开
标题翻译：可编程分支预测系统和计算机系统方法
公开(公告)号：JP2007058875A
公开(公告)日：2007-03-08
申请号：JP2006277835
申请日：2006-10-11
申请人： Jackie A Freeman , ジャッキーエイフリーマン
发明人： FREEMAN JACKIE A
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3844
摘要： PROBLEM TO BE SOLVED: To provide a programmable branch prediction system for preventing known device problems. SOLUTION: The system for predicting branches in a computer system is provided with: a memory containing program code comprising a plurality of instructions and prediction operations; a store containing a reference to a branch instruction in the program code and corresponding prediction data; a modification means for modifying the prediction data in response to the prediction operations contained within the program code; a prediction means for predicting an outcome of the branch instruction based on the prediction data to generate a prediction; and a means responsive to the prediction for predicting the outcome of the branch instruction. A method for predicting branches is also provided. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于防止已知设备问题的可编程分支预测系统。解决方案：用于预测计算机系统中的分支的系统被提供有：包含多个指令和预测操作的程序代码的存储器; 包含对程序代码中的分支指令的引用的存储器和对应的预测数据; 修改装置，用于响应于程序代码中包含的预测操作来修改预测数据; 预测装置，用于基于预测数据预测分支指令的结果以产生预测; 以及响应于预测分支指令的结果的装置。还提供了一种预测分支的方法。版权所有（C）2007，JPO＆INPIT

2. 发明授权

US06449712B1 Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions 失效
标题翻译：用较大的固定长度指令的序列来模拟执行较小的固定长度分支/延迟时隙指令
公开(公告)号：US06449712B1
公开(公告)日：2002-09-10
申请号：US09410851
申请日：1999-10-01
申请人： Naohiko Irie , Tony Lee Werner , Chih-Jui Peng , Sebastian H. Ziesler , Jackie A. Freeman , Sivaram Krishnan
发明人： Naohiko Irie , Tony Lee Werner , Chih-Jui Peng , Sebastian H. Ziesler , Jackie A. Freeman , Sivaram Krishnan
IPC分类号： G06F9455
CPC分类号： G06F9/30174 , G06F9/30058 , G06F9/3842
摘要： A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.
摘要翻译：构造为执行32位固定长度指令集体系结构的处理器元件向后兼容，用于通过将16位指令中的每一个转换为一个或多个32位的序列来执行16位固定长度指令集架构说明。 32位指令集架构包括“准备分支”指令，允许在分支之前设置分支指令的目标地址。组合32位准备到分支和分支指令以执行与16位延迟时隙指令相结合的16位分支指令。

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