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1. 发明授权

US08270239B2 Semiconductor memory device and methods of performing a stress test on the semiconductor memory device 失效
标题翻译：半导体存储器件以及对半导体存储器件进行应力测试的方法
公开(公告)号：US08270239B2
公开(公告)日：2012-09-18
申请号：US12330747
申请日：2008-12-09
申请人： Nan Chen , Changho Jung , Zhiqin Chen
发明人： Nan Chen , Changho Jung , Zhiqin Chen
IPC分类号： G11C29/50 , G11C29/06 , G11C29/00 , G11C11/41 , G11C11/413 , G11C8/08 , G11C7/12
CPC分类号： G11C29/50 , G11C11/41 , G11C29/24 , G11C2029/1204
摘要： A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode.
摘要翻译：提供一种在半导体存储器件上执行应力测试的半导体存储器件和方法。在一个示例中，半导体存储器件包括复用器装置，其被配置为在应力模式期间将控制半导体存储器件的内部定时的定时信号从内部信号切换到外部信号，并且还包括一个或多个字线在应力模式期间接收应力电压的半导体存储器件，基于外部信号的应力模式的持续时间。在另一示例中，半导体存储器件包括被配置为在应力模式期间接收应力电压的一个或多个字线，以及被配置为在应力模式期间向半导体存储器件的位线提供预充电电压的预充电电路。

2. 发明授权

US07948824B2 Self reset clock buffer in memory devices 有权
标题翻译：存储器中的自复位时钟缓冲器
公开(公告)号：US07948824B2
公开(公告)日：2011-05-24
申请号：US12792982
申请日：2010-06-03
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.
摘要翻译：存储器件包括时钟缓冲电路。时钟缓冲电路包括交叉耦合逻辑电路。交叉耦合逻辑电路具有至少两个逻辑门，其中至少一个逻辑门的输出耦合到至少一个逻辑门的输入。交叉耦合逻辑电路耦合到用于接受时钟信号的输入端。该存储器件还包括一个可从交叉耦合逻辑电路的输出产生时钟信号的时钟驱动器。从时钟信号到交叉耦合逻辑电路的反馈环路控制交叉耦合逻辑电路。包括三态反相器的缓冲电路耦合到时钟信号以保持时钟信号，同时避免与时钟发生器的争用。存储器件通过片选信号使能。

3. 发明申请

US20100142300A1 Semiconductor Memory Device And Methods Of Performing A Stress Test On The Semiconductor Memory Device 失效
标题翻译：半导体存储器件和在半导体存储器件上进行应力测试的方法
公开(公告)号：US20100142300A1
公开(公告)日：2010-06-10
申请号：US12330747
申请日：2008-12-09
申请人： Nan Chen , ChangHo Jung , Zhiqin Chen
发明人： Nan Chen , ChangHo Jung , Zhiqin Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/24 , G11C2029/1204
摘要： A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode.
摘要翻译：提供一种在半导体存储器件上执行应力测试的半导体存储器件和方法。在一个示例中，半导体存储器件包括复用器装置，其被配置为在应力模式期间将控制半导体存储器件的内部定时的定时信号从内部信号切换到外部信号，并且还包括一个或多个字线在应力模式期间接收应力电压的半导体存储器件，基于外部信号的应力模式的持续时间。在另一示例中，半导体存储器件包括被配置为在应力模式期间接收应力电压的一个或多个字线，以及被配置为在应力模式期间向半导体存储器件的位线提供预充电电压的预充电电路。

4. 发明授权

US08000165B2 Self reset clock buffer in memory devices 有权
公开(公告)号：US08000165B2
公开(公告)日：2011-08-16
申请号：US12207011
申请日：2008-09-09
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.

5. 发明申请

US20100226191A1 Leakage Reduction in Memory Devices 有权
标题翻译：内存设备中的泄漏减少
公开(公告)号：US20100226191A1
公开(公告)日：2010-09-09
申请号：US12397142
申请日：2009-03-03
申请人： Changho Jung , Nan Chen , Cheng Zhong , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Cheng Zhong , Zhiqin Chen
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/00 , G11C7/22 , G11C8/08 , G11C11/4094 , G11C11/413 , G11C2207/2227 , H03K19/0016
摘要： A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches are added for pre-charge devices to further reduce leakage current.
摘要翻译：存储器件包括包括存储器单元的核心阵列。存储器件还包括耦合到芯阵列的头灯和正电源电压。磁头开关通过将磁芯阵列与正电源电压断开来减少来自磁芯阵列的漏电流。另外，增加头开关用于预充电器件，以进一步减少泄漏电流。

6. 发明申请

US20100061161A1 Self Reset Clock Buffer In Memory Devices 有权
公开(公告)号：US20100061161A1
公开(公告)日：2010-03-11
申请号：US12207011
申请日：2008-09-09
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C7/00 , G11C8/18 , H03K19/00 , H03K3/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.

7. 发明申请

US20100238756A1 Self Reset Clock Buffer In Memory Devices 有权
标题翻译：内存器件中的自复位时钟缓冲器
公开(公告)号：US20100238756A1
公开(公告)日：2010-09-23
申请号：US12792982
申请日：2010-06-03
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C8/18 , H03K19/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.
摘要翻译：存储器件包括时钟缓冲电路。时钟缓冲电路包括交叉耦合逻辑电路。交叉耦合逻辑电路具有至少两个逻辑门，其中至少一个逻辑门的输出耦合到至少一个逻辑门的输入。交叉耦合逻辑电路耦合到用于接受时钟信号的输入端。该存储器件还包括一个可从交叉耦合逻辑电路的输出产生时钟信号的时钟驱动器。从时钟信号到交叉耦合逻辑电路的反馈环路控制交叉耦合逻辑电路。包括三态反相器的缓冲电路耦合到时钟信号以保持时钟信号，同时避免与时钟发生器的争用。存储器件通过芯片选择信号使能。

8. 发明授权

US08208316B2 SRAM yield enhancement by read margin improvement 有权
标题翻译：通过读取余量提高SRAM产量提高
公开(公告)号：US08208316B2
公开(公告)日：2012-06-26
申请号：US12194142
申请日：2008-08-19
申请人： Nan Chen , Chang Jung , Zhiqin Chen
发明人： Nan Chen , Chang Jung , Zhiqin Chen
IPC分类号： G11C7/06
CPC分类号： G11C7/12 , G11C11/409 , G11C2207/005
摘要： A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line.
摘要翻译：针对存储器阵列中的读取路径改进了检测边缘。实施例通过在读列多路复用器中使用具有较低阈值电压的门来提高感测余量。交叉耦合保持器可以通过增加存储高值的位线上的电压电平来进一步提高感测容限，从而抵消“高”位线上的泄漏。

9. 发明申请

US20090231934A1 Advanced Bit Line Tracking in High Performance Memory Compilers 有权
标题翻译：高性能内存编译器中的高级位线跟踪
公开(公告)号：US20090231934A1
公开(公告)日：2009-09-17
申请号：US12048676
申请日：2008-03-14
申请人： Chang Ho Jung , Nan Chen , Zhiqin Chen
发明人： Chang Ho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/14 , G11C7/08 , G11C7/22
摘要： A method accurately tracks a bit line maturing time for compiler memory. The method includes enabling a dummy word line in response to an internal clock signal. The dummy word line is enabled prior to enabling a real word line. A dummy bit line is matured in response to enabling of the dummy word line. The dummy bit line matures at a same rate that a real bit line matures. The method also includes disabling the dummy word line in response to determining a threshold voltage differential based on monitoring maturation of the dummy bit line. The real word line is enabled a predefined delay after enabling of the dummy word line. Similarly, the word line is disabled the predefined delay after disabling of the dummy word line. In response to disabling the dummy word line, a sense enable signal is generated.
摘要翻译：一种方法准确地跟踪编译器存储器的位线成熟时间。该方法包括响应于内部时钟信号启用伪字线。虚拟字线在启用实际字线之前被使能。虚拟位线响应于虚拟字线的使能而成熟。虚拟位线以与实际位线成熟的相同速率成熟。该方法还包括响应于基于虚拟位线的监视成熟确定阈值电压差来禁用该虚拟字线。在使能虚拟字线之后，实际字线被启用预定义的延迟。类似地，在禁用虚拟字线之后，字线被禁用预定义的延迟。响应于禁用虚拟字线，产生感测使能信号。

10. 发明申请

US20100146320A1 Memory Access Time Measurement Using Phase Detector 失效
标题翻译：使用相位检测器进行存储器访问时间测量
公开(公告)号：US20100146320A1
公开(公告)日：2010-06-10
申请号：US12328283
申请日：2008-12-04
申请人： Nan Chen , Zhiqin Chen , Varun Verma
发明人： Nan Chen , Zhiqin Chen , Varun Verma
IPC分类号： G06F1/12 , G06F1/14
CPC分类号： G11C29/50 , G01R31/31725 , G11C7/22 , G11C29/50012 , G11C29/56 , G11C29/56012
摘要： Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews.
摘要翻译：提供了用于确定存储器访问时间的方法和系统。在存储器使用的第一时钟信号和用作参考时钟信号的第二时钟信号之间测量第一相位偏移。然后，当存储器完成给定读取操作和第二时钟信号时，在由存储器输出的第一时钟信号的延迟版本之间测量第二相位偏移。存储器访问时间基于第一和第二相位偏移来确定。

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