会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明申请
    • Integrated online purchase reward system
    • 综合在线购买奖励制度
    • US20060089875A1
    • 2006-04-27
    • US10970934
    • 2004-10-22
    • Dae ParkChang JungBo LeeBrian Chung
    • Dae ParkChang JungBo LeeBrian Chung
    • G06Q30/00
    • G06Q30/02G06Q30/0222G06Q30/0226
    • An integrated online purchase reward system includes one or more first information processing devices, one or more second information processing devices, a network, and one or more purchase transaction monitoring devices which read in a purchase transaction medium, and print out purchase transaction records on the purchase transaction media as a hard copy. The first information processing devices receive, process, and distribute data, and respond to requests from the second information processing devices. The first information processing device includes database, and the second information processing devices are connected with the purchase transaction monitoring device. The network works on a TCP/IP Protocol environment and connects the first and the second information processing devices. The purchase transaction information including reward or gift is printed on a PET card through line thermal printing. A person with an appropriate authorization can access the first information processing device through internet and retrieve data.
    • 集成的在线购买奖励系统包括一个或多个第一信息处理设备,一个或多个第二信息处理设备,网络和在购买交易介质中读取的一个或多个购买交易监控设备,并且在 购买交易媒体作为硬拷贝。 第一信息处理设备接收,处理和分发数据,并响应来自第二信息处理设备的请求。 第一信息处理装置包括数据库,第二信息处理装置与购买交易监视装置连接。 该网络工作于TCP / IP协议环境,并连接第一和第二信息处理设备。 包括奖励或礼品在内的购买交易信息通过热敏打印印在PET卡上。 具有适当授权的人可以通过互联网访问第一信息处理设备并检索数据。
    • 3. 发明申请
    • Safety crampon with generality put on
    • 安全冰爪一般放在上面
    • US20060080861A1
    • 2006-04-20
    • US11241971
    • 2005-10-04
    • Wan ParkChang Jung
    • Wan ParkChang Jung
    • A43B15/00A43C15/00
    • A43B13/26A43B3/16A43B5/185A43C15/005A43C15/02A43C15/06
    • Disclosed is a safety crampon with generality put on, which encircles front/rear/left/right sides of shoes around a spike pad to elastically press and grip them so that the crampon is not come off from the shoes, thereby ensuring safety. Also, the safety crampon has excellent wearing feeling and walking owing to characteristics of an elastic material, can be put on all kinds of shoes including mountain-climbing boots, high-heeled shoes, and rubber shoes, allows a user to safely climb a mountain and safely walk on a skiddy icy road of the ground, and has a conveniently portable advantage. The antiskid safety crampon includes a spike pad made of an elastic material such as a foaming resin or rubber and provided with a plurality of spikes, a hook formed in the spike pad in a single body with the spike pad to be fixably hooked over shoes, a limb band oriented from four edges of the spike pad toward the contour, and a ring band inscribed in a front end of the limb band, wherein the spike pad, the hook, the limb band and the ring band are formed of an elastic material in a single body with one another.
    • 公开了一种通用的安全钳,其围绕钉垫周围的鞋子的前/后/左/右侧弹性地按压并夹紧,使得冰爪不会从鞋上脱落,从而确保安全。 此外,由于弹性材料的特点,安全钳具有优异的穿着感和行走能力,可以放在各种鞋子上,包括登山靴,高跟鞋和橡胶鞋,允许用户安全地爬山 并安全地走在地面上冰冷的冰冷的道路上,具有方便便携的优点。 防滑安全系统包括由诸如发泡树脂或橡胶的弹性材料制成的钉垫,并且设置有多个钉,钩形成在单个主体中的钉垫中,钉垫可固定地钩在鞋上, 从所述尖钉垫的四个边缘朝向轮廓定向的肢体带,以及内嵌在所述肢体带的前端中的环带,其中所述钉垫,钩,所述肢带和所述环带由弹性材料形成 在一个单一的身体彼此。
    • 6. 发明申请
    • Method of designing a micro-bts
    • 微电脑设计方法
    • US20070004458A1
    • 2007-01-04
    • US10560149
    • 2004-07-23
    • Chang Jung
    • Chang Jung
    • H04B1/38
    • H04B1/406
    • The present invention relates to a method of designing a micro-Base Transceiver System (BTS) of a CDMA system. In a conventional micro-BTS, one Intermediate Frequency (IF) board has only one sector or Frequency Assignment (FA) therein, and a digital combiner and a switching logic are comprised in individual channel cards and IF boards. Thus, the FA to an IF board cannot avoid being fixed. However, according to the present invention, a digital combiner and a switching logic are transplanted in a main board of a micro-BTS, which operates as a backplane. By using this construction, the present invention can achieve a more efficient interface between a channel card and an IF board, and further increase the flexibility in establishing FAs.
    • 本发明涉及CDMA系统的微型基站收发系统(BTS)的设计方法。 在传统的微型BTS中,一个中频(IF)板在其中仅具有一个扇区或频率分配(FA),并且数字组合器和开关逻辑包括在各个通道卡和IF板中。 因此,中信证券董事会的FA不能避免被修正。 然而,根据本发明,数字组合器和开关逻辑被移植到作为背板操作的微BTS的主板中。 通过使用这种结构,本发明可以实现通道卡和IF板之间的更有效的接口,并进一步提高建立FA的灵活性。
    • 7. 发明授权
    • Metal programmable self-timed memories
    • 金属可编程自定时存储器
    • US07746722B2
    • 2010-06-29
    • US12140502
    • 2008-06-17
    • Jeffrey Scott BrownChang Jung
    • Jeffrey Scott BrownChang Jung
    • G11C8/00
    • G11C8/10G11C5/025G11C11/417
    • A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.
    • 公开了一种自定时存储器阵列,其中支持可分割性和金属可编程性,同时最小化布局空间。 自定时行解码器电路放置在与相应I / O块相邻的阵列的顶部和底部。 自定时信号从阵列的顶部(相应的底部)路由到存储器阵列的中途(分别向上)一点,然后返回到顶部(相应的底部)的自定时行解码器 阵列。 也可以使用相同的方法来解释从阵列的底部(相对顶部)到I / O块中的读出放大器的位线延迟。 通过从不需要的存储器单元中消除金属布线层来提供电线布线的进一步的灵活性,并且可以使用可编程门阵列来允许为存储器选择任意的字大小。
    • 8. 发明申请
    • METAL PROGRAMMABLE SELF-TIMED MEMORIES
    • 金属可编程自定义记忆
    • US20080253206A1
    • 2008-10-16
    • US12140502
    • 2008-06-17
    • Jeffrey Scott BrownChang Jung
    • Jeffrey Scott BrownChang Jung
    • G11C7/00G06F17/50
    • G11C8/10G11C5/025G11C11/417
    • A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.
    • 公开了一种自定时存储器阵列,其中支持可分割性和金属可编程性,同时最小化布局空间。 自定时行解码器电路放置在与相应I / O块相邻的阵列的顶部和底部。 自定时信号从阵列的顶部(相应的底部)路由到存储器阵列的中途(分别向上)一点,然后返回到顶部(相应的底部)的自定时行解码器 阵列。 也可以使用相同的方法来解释从阵列的底部(相对顶部)到I / O块中的读出放大器的位线延迟。 通过从不需要的存储器单元中消除金属布线层来提供电线布线的进一步的灵活性,并且可以使用可编程门阵列来允许为存储器选择任意的字大小。
    • 9. 发明申请
    • Pseudo-dual port memory having a clock for each port
    • 伪双端口存储器具有每个端口的时钟
    • US20070109884A1
    • 2007-05-17
    • US11282345
    • 2005-11-17
    • Chang Jung
    • Chang Jung
    • G11C29/00
    • G11C7/22G11C7/1012G11C7/1051G11C7/1075G11C7/1078G11C7/1093G11C7/222G11C8/16G11C2207/108G11C2207/2281G11C2207/229
    • A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.
    • 伪双端口存储器具有第一端口,第二端口和六晶体管存储器单元的阵列。 在接收到第一端口上的第一时钟信号的上升沿开始第一存储器访问。 响应于接收到第二端口的第二时钟信号的上升沿来启动第二存储器访问。 如果第二时钟信号的上升沿在第一时间段内发生,则在伪双端口方式完成第一存储器访问之后立即启动第二存储器访问。 如果第二时钟信号的上升沿在第二时间段内稍后发生,则第二存储器访问被延迟直到第一时钟信号的第二上升沿。 第一和第二存储器访问的持续时间不依赖于时钟信号的占空比。
    • 10. 发明申请
    • Apparatus and method of receiving digital multimedia broadcasting
    • 数字多媒体广播接收装置及方法
    • US20060250528A1
    • 2006-11-09
    • US11394530
    • 2006-03-30
    • Chang Jung
    • Chang Jung
    • H04N5/268H04N5/60
    • H04N5/268H04H60/27H04N21/42615H04N21/434H04N21/4383
    • Disclosed are an apparatus and a method of receiving a digital multimedia broadcasting (DMB). According to the invention, there is provided a storage buffer capable of temporarily storing each of the received DMB channel signals and the specific contents signals selected by the user irrespective of whether the DMB channels are same to each other or not are outputted, among the contents signals (for example, video signal, audio signal and data signal) contained in each of the DMB channel signals temporarily stored. Accordingly, the user can see and hear the contents signals of the different channels (for example, a combination of video signal of channel A and audio signal of channel B) outputted through a screen and a speaker at the same time depending on the user's tastes.
    • 公开了一种接收数字多媒体广播(DMB)的装置和方法。 根据本发明,提供了一种存储缓冲器,其能够临时存储接收到的DMB信道信号和用户选择的特定内容信号,而不管DMB信道是否彼此相同。 包含在临时存储的每个DMB信道信号中的信号(例如,视频信号,音频信号和数据信号)。 因此,根据用户的口味,用户可以同时观看和听到通过屏幕和扬声器输出的不同频道的内容信号(例如,通道A的视频信号和通道B的音频信号的组合) 。