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1. 发明授权

US5892895A Method an apparatus for tolerance of lost timer ticks during recovery of a multi-processor system 失效
标题翻译：方法在恢复多处理器系统期间容忍丢失定时器滴答的装置
公开(公告)号：US5892895A
公开(公告)日：1999-04-06
申请号：US790268
申请日：1997-01-28
申请人： Murali Basavaiah , Karoor S. Krishnakuma , Srinivasa D. Murthy
发明人： Murali Basavaiah , Karoor S. Krishnakuma , Srinivasa D. Murthy
IPC分类号： G06F11/20 , G06F11/00 , G06F11/14
CPC分类号： H04L69/28 , G06F11/1425 , H04L69/40
摘要： A method and apparatus for detecting and tolerating situations in which one or more processors in a multi-processor system cannot participate in timer-driven or timer-triggered protocols or event sequences. The multi-processor system includes multiple processors each having a respective memory. These processors are coupled by an inter-processor communication network (preferably consisting of redundant paths).Processors are suspected of having failed (ceased operations) outright or having a failed timer mechanism when other processors detect the absence of periodic "IamAlive" messages from other processors. When this happens, all of the processors in the system are subjected to a series of stages in which they repeatedly broadcast their status and their connectivity to each other. During the first such stage, according to the present invention, a processor will not assert its ability to participate unless its timer mechanism is working. It arms a timer expiration event and does not assert its health until and unless that timer expiration event occurs.
摘要翻译：一种用于检测和容忍多处理器系统中的一个或多个处理器不能参与定时器驱动或定时器触发的协议或事件序列的情况的方法和装置。多处理器系统包括多个具有相应存储器的处理器。这些处理器通过处理器间通信网络（优选地由冗余路径组成）耦合。当其他处理器检测到不存在来自其他处理器的周期性“IamAlive”消息时，处理器被怀疑已经失败（停止操作）或定时器机制失败。当这种情况发生时，系统中的所有处理器都经历一系列阶段，在这些阶段中，它们重复地广播其状态及其彼此的连接。在第一个这样的阶段期间，根据本发明，处理器将不会断言其参与的能力，除非其定时器机制正在工作。它会阻止定时器到期事件，并且除非发生定时器到期事件，否则不会断言其状态。

2. 发明授权

US5884018A Method and apparatus for distributed agreement on processor membership in a multi-processor system 失效
标题翻译：多处理器系统中处理器成员资格分配协议的方法和装置
公开(公告)号：US5884018A
公开(公告)日：1999-03-16
申请号：US789257
申请日：1997-01-28
申请人： Robert L. Jardine , Murali Basavaiah , Karoor S. Krishnakumar , Srinivasa D. Murthy
发明人： Robert L. Jardine , Murali Basavaiah , Karoor S. Krishnakumar , Srinivasa D. Murthy
IPC分类号： G06F11/20 , G06F11/00 , G06F11/14 , G06F13/00
CPC分类号： G06F11/0724 , G06F11/1425 , G06F11/0757
摘要： An apparatus and protocol to determine the group of processors that will survive communications faults and/or timed-event failures in a multiprocessor system. The processors each have a respective memory, and the processors are coupled by means of an inter-processor communication network. The processors detect that the set of processors with which they can communicate has changed. They can choose to either halt or continue operations based on minimizing the likelihood that disconnected groups of processors will continue to operate as independent systems. The processors construct a connectivity matrix on the initiation of a regroup operation. The connectivity information is used to ensure that all the processors in the final group that survives can communicate with all other processors in the group. One or more processors may halt to achieve this characteristic. A processor is suspected of having ceased operations or having a failed timer mechanism when other processors detect the absence of a periodic message from the processor. When this happens, all of the processors are subjected to a series of stages in which they repeatedly broadcast their status and connectivity to each other. The suspected processor does not advance through the stages if it has ceased operations or if its timer mechanism has failed.
摘要翻译：一种用于确定能够在多处理器系统中的通信故障和/或定时事件故障中存活的处理器组的装置和协议。处理器各自具有相应的存储器，并且处理器通过处理器间通信网络耦合。处理器检测到他们可以通信的一组处理器已经改变了。它们可以选择停止或继续操作，这是基于最小化不连续的处理器组作为独立系统继续运行的可能性。处理器在重组操作的启动时构建连接矩阵。连接信息用于确保最终组中存在的所有处理器可以与组中的所有其他处理器通信。一个或多个处理器可以停止以实现该特性。当其他处理器检测到处理器不存在周期性消息时，处理器被怀疑已经停止操作或发生故障定时器机制。当这种情况发生时，所有处理器都经历一系列的阶段，在这些阶段中，它们重复地将其状态和连接相互广播。怀疑的处理器如果停止运行或者其定时器机制失败，则不会进入阶段。

3. 发明申请

US20130290642A1 Managing nodes in a storage system 有权
公开(公告)号：US20130290642A1
公开(公告)日：2013-10-31
申请号：US13459240
申请日：2012-04-29
申请人： Hueichian Huang , Srinivasa D. Murthy , Siamak Nazari , Roopesh Kumar Tamma , Jianding Luo
发明人： Hueichian Huang , Srinivasa D. Murthy , Siamak Nazari , Roopesh Kumar Tamma , Jianding Luo
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F3/067 , G06F3/0617 , G06F3/0631 , G06F3/0665
摘要： Each node in a clustered array is the owner of a set of zero logical disks (LDs). Thinly-provisioned VVs (TPVVs) are partitioned so each is mapped to a group of zero LDs from different sets of zero LDs. When there is a change in ownership, the affected zero LDs are switched one at a time so only a group of the TPVVs is affected each time.

4. 发明授权

US5805920A Direct bulk data transfers 失效
标题翻译：直接批量数据传输
公开(公告)号：US5805920A
公开(公告)日：1998-09-08
申请号：US556618
申请日：1995-11-13
申请人： Todd W. Sprenkle , Srinivasa D. Murthy , Anil Khatri
发明人： Todd W. Sprenkle , Srinivasa D. Murthy , Anil Khatri
IPC分类号： G06F15/16 , G06F9/46 , G06F11/20 , G06F15/177 , G06F13/00
CPC分类号： G06F9/544 , G06F11/2035 , G06F11/2046 , G06F11/2071 , G06F11/2089
摘要： A data processing system for transferring data is provided. This system includes central processing units (CPUs 20, 22, 24 and 26) and storage units (30 and 32 with 100-105 and 110-115) which are interconnected by a network (10). The CPUs (20, 22, 24 and 26) include a request process (133) and a storage process (130). The storage process (130) controls access to the storage unit (30 with 100-105 and 110-115). Software routines (220) are used to provide direct access to the storage unit (30 with 100-105 and 110-115) by the request CPU (22). The request CPU (20) is the CPU containing the request process (133). A virtual memory address for a buffer (160) of the request CPU (22) is created in the request CPU (22). The virtual memory address along with a storage unit access request are sent to the CPU (20) containing the storage process (130). A work request including the virtual memory address to sent from the storage process (130) to the storage unit (30 with 100-105 and 110-115). The data is then transferred directly between the request CPU (22) and the storage unit (30 with 100-105 and 110-115). The storage unit (30 with 100-105 and 110-115) then responds to the work request.
摘要翻译：提供了一种用于传送数据的数据处理系统。该系统包括由网络（10）互连的中央处理单元（CPU 20,22,24和26）以及具有100-105和110-115的存储单元（30和32）。 CPU（20,22,24和26）包括请求处理（133）和存储处理（130）。存储处理（130）控制对具有100-105和110-115的存储单元（30）的访问。软件程序（220）用于通过请求CPU（22）直接访问具有100-105和110-115的存储单元（30）。请求CPU（20）是包含请求处理（133）的CPU。在请求CPU（22）中创建请求CPU（22）的缓冲器（160）的虚拟存储器地址。虚拟存储器地址以及存储单元访问请求被发送到包含存储处理（130）的CPU（20）。一种工作请求，其包括从存储处理（130）发送到存储单元（30-10，具有100-105和110-115）的虚拟存储器地址。然后，数据直接在请求CPU（22）和存储单元（30〜100〜105和110-115）之间传送。存储单元（30与100-105和110-115）然后响应工作请求。

5. 发明授权

US5577261A Ordered and reliable maintenance of inter-process relationships in a distributed multiprocessor 失效
标题翻译：在分布式多处理器中有序且可靠地维护进程间关系
公开(公告)号：US5577261A
公开(公告)日：1996-11-19
申请号：US377386
申请日：1995-01-23
申请人： Venkatesh Harinarayan , Srinivasa D. Murthy , Alan L. Rowe
发明人： Venkatesh Harinarayan , Srinivasa D. Murthy , Alan L. Rowe
IPC分类号： G06F11/20 , G06F9/46 , G06F9/52 , G06F11/00 , G06F11/14 , G06F13/14
CPC分类号： G06F11/1482 , G06F11/1425 , G06F9/52 , G06F2201/82 , G06F2201/825
摘要： An apparatus and method, using an inter-processor lock to control access to inter-process relationship data structures in the memory of each processor in a multiprocessor system. The apparatus and method insure that each inter-process relationship is modified in the same sequence on each processor. The apparatus and method also insure that an inter-process relationship is maintained in a consistent state in the face of failure of any of the processors.
摘要翻译：一种装置和方法，使用处理器间锁来控制对多处理器系统中每个处理器的存储器中的处理间关系数据结构的访问。该装置和方法确保在每个处理器上以相同的顺序修改每个进程间关系。该装置和方法还确保在任何处理器的故障的情况下，处理间关系被保持在一致的状态。

6. 发明授权

US5968134A Distributed pipes and fifos in a multiprocessor 失效
标题翻译：分布式管道和fifos在多处理器中
公开(公告)号：US5968134A
公开(公告)日：1999-10-19
申请号：US947495
申请日：1997-10-03
申请人： Franco Putzolu , Srinivasa D. Murthy , Alan M. Usas , Gary F. Tom , Minoo Gupta , Eric G. Strellis
发明人： Franco Putzolu , Srinivasa D. Murthy , Alan M. Usas , Gary F. Tom , Minoo Gupta , Eric G. Strellis
IPC分类号： G06F12/00 , G06F9/46 , G06F9/54 , G06F17/30 , G06F15/163
CPC分类号： G06F9/544 , G06F17/30067
摘要： A multiprocessor that includes a virtual file system providing a file system interface to user application code. This interface allows users to access files in many types of file systems in a consistent, file system-independent manner. In a preferred embodiment, the higher interface of the file system is the Posix file system interface, though it can be any file system interface supporting the capabilities required by a user process. The Posix file system supports regular files, pipes, fifos and special files.A pipe server, a pipe library and a name server together implement the fifo semantics required by the Posix standard for Posix processes. The present invention provides these fifo capabilities to any process which uses the Posix interfaces.
摘要翻译：一个多处理器，包括一个虚拟文件系统，提供用户应用程序代码的文件系统接口。该界面允许用户以一致的文件系统独立方式访问许多类型的文件系统中的文件。在优选实施例中，文件系统的较高接口是Posix文件系统接口，尽管它可以是支持用户进程所需的能力的任何文件系统接口。 Posix文件系统支持常规文件，管道，fifos和特殊文件。一个管道服务器，一个管道库和一个名称服务器一起实现Posix标准所要求的fifo语义。本发明为使用Posix接口的任何进程提供这些fifo能力。

7. 发明授权

US5794034A Ordered and reliable maintenance of inter-process relationships in a distributed multiprocessor 失效
公开(公告)号：US5794034A
公开(公告)日：1998-08-11
申请号：US935617
申请日：1997-09-23
申请人： Venkatesh Harinarayan , Srinivasa D. Murthy , Alan L. Rowe
发明人： Venkatesh Harinarayan , Srinivasa D. Murthy , Alan L. Rowe
IPC分类号： G06F11/20 , G06F9/46 , G06F9/52 , G06F11/00 , G06F11/14 , G06F13/14
CPC分类号： G06F11/1482 , G06F11/1425 , G06F9/52 , G06F2201/82 , G06F2201/825
摘要： An apparatus and method, using an inter-processor lock to control access to inter-process relationship data structures in the memory of each processor in a multiprocessor system. The apparatus and method insure that each inter-process relationship is modified in the same sequence on each processor. The apparatus and method also insure that an inter-process relationship is maintained in a consistent state in the face of failure of any of the processors.

8. 发明授权

US5630140A Ordered and reliable signal delivery in a distributed multiprocessor 失效
标题翻译：在分布式多处理器中有序可靠的信号传送
公开(公告)号：US5630140A
公开(公告)日：1997-05-13
申请号：US377387
申请日：1995-01-23
申请人： Ramin Modiri , Srinivasa D. Murthy , Alan L. Rowe
发明人： Ramin Modiri , Srinivasa D. Murthy , Alan L. Rowe
IPC分类号： G06F11/20 , G06F9/46 , G06F9/52 , G06F11/00 , G06F11/14 , G06F13/14
CPC分类号： G06F11/2023 , G06F11/1443 , G06F9/542
摘要： An apparatus and method, using an inter-processor lock to coordinate signal delivery to a process group whose member processes are distributed across multiple processors. The apparatus and method insure that each process group member process receives the same signals in the same order and that no signal is duplicated. The apparatus and method also insure that a partially completed signal delivery is completed even in the face of failure of the signalling processor.
摘要翻译：一种装置和方法，使用处理器间协调处理器锁定信号传递给成员进程分布在多个处理器上的进程组。该装置和方法确保每个进程组成员进程以相同的顺序接收相同的信号，并且不复制任何信号。该装置和方法还确保即使面对信令处理器的故障也完成部分完成的信号传递。

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