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1. 发明授权

US07265396B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07265396B2
公开(公告)日：2007-09-04
申请号：US11027058
申请日：2004-12-29
申请人： Muneaki Maeno , Toshiki Morimoto , Hiroaki Suzuki
发明人： Muneaki Maeno , Toshiki Morimoto , Hiroaki Suzuki
IPC分类号： H01L27/10
CPC分类号： H01L27/11807
摘要： A basic cell placed in a semiconductor device comprises a via contact placed on a wiring grid having a pitch narrower than a pitch between a contact placed in a source region and a contact placed in a drain region of a transistor in a basic cell, and a wiring layer connected to the via contact, being used as a source terminal, a drain terminal, and a gate terminal of the transistor.
摘要翻译：放置在半导体器件中的基本单元包括放置在布线栅格上的通孔接点，该布线栅格具有比放置在源极区域中的接触点与设置在基本单元中的晶体管的漏极区域中的接点之间的间距窄的间距，连接到通孔触点的布线层，用作晶体管的源极端子，漏极端子和栅极端子。

2. 发明申请

US20050145887A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050145887A1
公开(公告)日：2005-07-07
申请号：US11027058
申请日：2004-12-29
申请人： Muneaki Maeno , Toshiki Morimoto , Hiroaki Suzuki
发明人： Muneaki Maeno , Toshiki Morimoto , Hiroaki Suzuki
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/10 , H01L27/118
CPC分类号： H01L27/11807
摘要： A basic cell placed in a semiconductor device comprises a via contact placed on a wiring grid having a pitch narrower than a pitch between a contact placed in a source region and a contact placed in a drain region of a transistor in a basic cell, and a wiring layer connected to the via contact, being used as a source terminal, a drain terminal, and a gate terminal of the transistor.
摘要翻译：放置在半导体器件中的基本单元包括放置在布线栅格上的通孔接点，该布线栅格具有比放置在源极区域中的接触点与设置在基本单元中的晶体管的漏极区域中的接点之间的间距窄的间距，连接到通孔触点的布线层，用作晶体管的源极端子，漏极端子和栅极端子。

3. 发明授权

US06849906B2 Standard-cell type semiconductor integrated circuit device with a mixed arrangement of standard cells differing in height 失效
标题翻译：具有高度不同的标准电池的混合布置的标准电池型半导体集成电路器件
公开(公告)号：US06849906B2
公开(公告)日：2005-02-01
申请号：US10365415
申请日：2003-02-12
申请人： Muneaki Maeno , Toshiki Morimoto
发明人： Muneaki Maeno , Toshiki Morimoto
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/06 , H01L27/118 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L31/62
CPC分类号： H01L27/11807
摘要： A first cell block in which a plurality of standard cells with a large cell height are arranged and a second cell block in which a plurality of standard cells with a small cell height are arranged. In the second cell block, transistors are formed whose shape and characteristics are practically the same as those of the transistors provided in the standard cells with the large cell height arranged in the first cell block.
摘要翻译：布置有多个具有大单元高度的标准单元的第一单元块和布置有小单元高度的多个标准单元的第二单元块。在第二单元块中，形成晶体管，其晶体管的形状和特性与设置在第一单元块中的具有大单元高度的标准单元中提供的晶体管的形状和特性实际上相同。

4. 发明授权

US08030773B2 Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy 有权
标题翻译：半导体集成电路器件包括由导体层连接的不同级别的互连层，包括用于冗余的导体层
公开(公告)号：US08030773B2
公开(公告)日：2011-10-04
申请号：US11752999
申请日：2007-05-24
申请人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
发明人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
摘要翻译：第三互连层设置在第一互连层附近，以及布置在第一互连层上方的第二互连层。第一互连层和第二互连层通过常规的通孔插头和通孔插头相互连接，用于冗余。用于冗余的通孔插头由正常通孔插头的侧面和正常通孔插头和第三互连层之间设置。第二互连层的延伸部分从连接到通孔插头的部分延伸，以在第二互连层上朝向第三互连层冗余。延伸部分具有小于互连线设计规则中规定的最小尺寸的尺寸。

5. 发明申请

US20060199325A1 Semiconductor integrated circuit device advantageous for microfabrication and manufacturing method for the same 审中-公开
标题翻译：有利于微加工的半导体集成电路器件及其制造方法
公开(公告)号：US20060199325A1
公开(公告)日：2006-09-07
申请号：US11365087
申请日：2006-02-28
申请人： Muneaki Maeno , Toshikazu Sei
发明人： Muneaki Maeno , Toshikazu Sei
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L27/11807
摘要： A semiconductor integrated circuit device includes cells, each of the cells including a gate electrode, which is provided on the well, and first diffusion layers of a second conductivity type which are provided in the well such that the first diffusion layers sandwich the gate electrode, the first diffusion layers functioning as sources/drains. The device further includes sub-regions which are arranged in a non-occupied area of the logic circuit structure region, each of the sub-regions including a conductive layer, which is provided on the well and has the same pattern shape as the gate electrode, and second diffusion layers of the first conductivity type, which have the same pattern shape as the first diffusion layers and are disposed spaced apart to sandwich the conductive layer, the second diffusion layers being electrically connected to the well.
摘要翻译：半导体集成电路器件包括单元，每个单元包括设置在阱上的栅电极和设置在阱中的第二导电类型的第一扩散层，使得第一扩散层夹着栅电极，第一扩散层用作源/排水管。该器件还包括布置在逻辑电路结构区域的非占用区域中的子区域，每个子区域包括导体层，该导电层设置在阱上并具有与栅电极相同的图案形状以及第一导电类型的第二扩散层，其具有与第一扩散层相同的图案形状并且间隔设置以夹持导电层，第二扩散层电连接到阱。

6. 发明授权

US06753611B1 Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program 有权
公开(公告)号：US06753611B1
公开(公告)日：2004-06-22
申请号：US09658452
申请日：2000-09-08
申请人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
发明人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

7. 发明申请

US20070273028A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE COMPRISING DIFFERENT LEVEL INTERCONNECTION LAYERS CONNECTED BY CONDUCTOR LAYERS INCLUDING CONDUCTOR LAYER FOR REDUNDANCY 有权
标题翻译：包含由导体层连接的不同级别互连层的半导体集成电路器件，包括用于冗余的导体层
公开(公告)号：US20070273028A1
公开(公告)日：2007-11-29
申请号：US11752999
申请日：2007-05-24
申请人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
发明人： Nobuhiko Kurata , Kouichirou Inoue , Shinji Fujii , Muneaki Maeno
IPC分类号： H01L23/52
CPC分类号： H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
摘要翻译：第三互连层设置在第一互连层附近，以及布置在第一互连层上方的第二互连层。第一互连层和第二互连层通过常规的通孔插头和通孔插头相互连接，用于冗余。用于冗余的通孔插头由正常通孔插头的侧面和正常通孔插头和第三互连层之间设置。第二互连层的延伸部分从连接到通孔插头的部分延伸，以在第二互连层上朝向第三互连层冗余。延伸部分具有小于互连线设计规则中规定的最小尺寸的尺寸。

8. 发明授权

US07444614B2 Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal 有权
标题翻译：存储半导体设计程序的计算机可读记录介质，用于改善通孔接触和金属的集成和连接
公开(公告)号：US07444614B2
公开(公告)日：2008-10-28
申请号：US10968925
申请日：2004-10-21
申请人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
发明人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
IPC分类号： G06F17/50 , H01L23/52
CPC分类号： H01L23/5226 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.
摘要翻译：半导体器件具有通孔接触，主线的端部连接到通孔接触，以及从主线的端部延伸成与主线成直线延伸超过通孔接触的延伸部，延伸部的宽度等于或窄于主导线的宽度。该延伸部通过光学接近效应防止主线的端部变圆，消除了通孔接触和主线的端部之间的接触缺陷或开放缺陷，并且不涉及导线围绕通孔的变宽 - 接触，使得其他通孔接触可以布置在所述通孔接触的附近，而不违反设计规则。

9. 发明申请

US20060012050A1 Semiconductor device, designing method thereof, and recording medium storing semicondcutor designing program 有权
标题翻译：半导体器件，其设计方法以及存储半衰落设计程序的记录介质
公开(公告)号：US20060012050A1
公开(公告)日：2006-01-19
申请号：US10968925
申请日：2004-10-21
申请人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
发明人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.
摘要翻译：半导体器件具有通孔接触，主线的端部连接到通孔接触，以及从主线的端部延伸成与主线成直线延伸超过通孔接触的延伸部，延伸部的宽度等于或窄于主导线的宽度。该延伸部通过光学接近效应防止主线的端部变圆，消除了通孔接触和主线的端部之间的接触缺陷或开放缺陷，并且不涉及导线围绕通孔的变宽 - 接触，使得其他通孔接触可以布置在所述通孔接触的附近，而不违反设计规则。

10. 发明授权

US06826742B2 Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program 有权
标题翻译：半导体器件，其设计方法和存储半导体设计程序的记录介质
公开(公告)号：US06826742B2
公开(公告)日：2004-11-30
申请号：US10675957
申请日：2003-10-02
申请人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
发明人： Muneaki Maeno , Kenji Kimura , Toshikazu Sei
IPC分类号： G06F1750
CPC分类号： H01L23/5226 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.
摘要翻译：半导体器件具有通孔接触，主线的端部连接到通孔接触，以及从主线的端部延伸成与主线成直线延伸超过通孔接触的延伸部，延伸部的宽度等于或窄于主导线的宽度。该延伸部通过光学接近效应防止主线的端部变圆，消除了通孔接触和主线的端部之间的接触缺陷或开放缺陷，并且不涉及导线围绕通孔的变宽 - 接触，使得其他通孔接触可以布置在所述通孔接触的附近，而不违反设计规则。

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