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1. 发明授权

US08653852B2 Voltage level shifter with dynamic circuit structure having discharge delay tracking 失效
标题翻译：具有放电延迟跟踪的动态电路结构的电压电平移位器
公开(公告)号：US08653852B2
公开(公告)日：2014-02-18
申请号：US13047331
申请日：2011-03-14
申请人： Jentsung Lin , Paul Douglas Bassett
发明人： Jentsung Lin , Paul Douglas Bassett
IPC分类号： H03K19/0175 , H03K19/096
CPC分类号： H03K19/018521 , H03K19/01728 , H03K19/01855 , H03K19/0963
摘要： In a particular embodiment, an apparatus includes a a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit.
摘要翻译：在一个具体实施例中，一种装置包括动态电路结构，其包括耦合预充电电路的动态节点，放电电路和门控保持器电路。门控保护器电路由来自放电延迟跟踪电路的信号使能。

2. 发明授权

US08527825B2 Debugger based memory dump using built in self test 失效
标题翻译：基于调试器的内存转储使用内置的自检
公开(公告)号：US08527825B2
公开(公告)日：2013-09-03
申请号：US12886629
申请日：2010-09-21
申请人： Hong S. Kim , Paul F. Policke , Paul Douglas Bassett
发明人： Hong S. Kim , Paul F. Policke , Paul Douglas Bassett
IPC分类号： G01R31/28
CPC分类号： G06F11/3656
摘要： A method and apparatus for performing a memory dump. The method includes providing a memory location from a debugger to a memory array through a BIST wrapper, and receiving data by the debugger read from the memory location in the memory array. The method can include sending a dump enable signal from the debugger, and the BIST wrapper selectively providing the memory location to the memory array in response to the dump enable signal. The method can include sending the dump enable signal to a multiplexer coupled to a register in the BIST wrapper, the dump enable signal causing the multiplexer to load the register with the memory location. The method can include asynchronously sending a write disable signal to the memory array before reading the data from the memory location. The received data can be selected from a larger set of data read from the memory location.
摘要翻译：一种用于执行存储器转储的方法和装置。该方法包括通过BIST包装器从调试器提供存储器位置到存储器阵列，以及通过从存储器阵列中的存储器位置读取的调试器接收数据。该方法可以包括从调试器发送转储使能信号，并且BIST封装器响应于转储使能信号而选择性地将存储器位置提供给存储器阵列。该方法可以包括将转储使能信号发送到耦合到BIST封装中的寄存器的多路复用器，转储使能信号使多路复用器将存储器位置加载寄存器。该方法可以在从存储器位置读取数据之前异步地向存储器阵列发送写禁止信号。所接收的数据可以从从存储器位置读取的较大数据集中选择。

3. 发明授权

US08466707B2 Method and apparatus for testing a memory device 失效
标题翻译：用于测试存储器件的方法和装置
公开(公告)号：US08466707B2
公开(公告)日：2013-06-18
申请号：US12716341
申请日：2010-03-03
申请人： Baker S. Mohammad , Hong S. Kim , Paul Douglas Bassett
发明人： Baker S. Mohammad , Hong S. Kim , Paul Douglas Bassett
IPC分类号： G01R31/02
CPC分类号： G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
摘要： In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
摘要翻译：在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。该偏压由对控制器作出响应的偏置电路提供。当井被偏置时，执行半导体器件的测试以产生测试数据。

4. 发明申请

US20120124433A1 Feedback Scan Isolation and Scan Bypass Architecture 有权
标题翻译：反馈扫描隔离和扫描旁路架构
公开(公告)号：US20120124433A1
公开(公告)日：2012-05-17
申请号：US12944090
申请日：2010-11-11
申请人： Paul F. Policke , Hong S. Kim , Paul Douglas Bassett
发明人： Paul F. Policke , Hong S. Kim , Paul Douglas Bassett
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318558 , G01R31/318572
摘要： A feedback scan isolation and bypass architecture apparatus and method. The apparatus includes core logic, and input and output multiplexers. The input multiplexer selectively provides a functional input or the core output to the core input based on a test signal. The output multiplexer selectively provides the core output or the input multiplexer output to a functional output based on the test signal. When the test signal indicates core feedback testing, the output multiplexer outputs the core output and the input multiplexer feeds back the core output to the core input. When the test signal indicates bypass testing, the input multiplexer outputs the functional input and the output multiplexer outputs the functional input bypassing the core logic. Logic can block the feedback or bypass signals when there are timing issues. Logic can modify the number of feedback or bypass signals when the number of functional inputs and outputs are different.
摘要翻译：反馈扫描隔离和旁路架构设备和方法。该装置包括核心逻辑，以及输入和输出多路复用器。输入复用器基于测试信号选择性地向核心输入提供功能输入或核心输出。输出复用器基于测试信号选择性地将核心输出或输入多路复用器输出提供给功能输出。当测试信号指示核心反馈测试时，输出多路复用器输出核心输出，输入多路复用器将核心输出反馈到核心输入。当测试信号指示旁路测试时，输入多路复用器输出功能输入，输出多路复用器输出旁路核心逻辑的功能输入。当有时序问题时，逻辑可以阻止反馈或旁路信号。当功能输入和输出数量不同时，逻辑可以修改反馈或旁路信号的数量。

5. 发明申请

US20100228944A1 Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode 失效
标题翻译：在Base Plus偏移寻址模式中将虚拟地址转换为物理地址的装置和方法
公开(公告)号：US20100228944A1
公开(公告)日：2010-09-09
申请号：US12397438
申请日：2009-03-04
申请人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
发明人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译：公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。

6. 发明授权

US08522097B2 Logic built-in self-test programmable pattern bit mask 失效
标题翻译：逻辑内置自检可编程模式位掩码
公开(公告)号：US08522097B2
公开(公告)日：2013-08-27
申请号：US12724527
申请日：2010-03-16
申请人： Hong S. Kim , Paul F. Policke , Paul Douglas Bassett
发明人： Hong S. Kim , Paul F. Policke , Paul Douglas Bassett
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318533 , G01R31/318555
摘要： In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built-in self-test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.
摘要翻译：在特定实施例中，公开了一种方法，其包括将多个扫描链内的故障比特位置映射到存储器掩码的存储器位置。该方法还包括使用存储器掩模在半导体器件上执行逻辑内置自检（LBIST）测试，以选择性地掩盖多个扫描链中的某些结果。结果与半导体器件上LBIST测试的性能相关。

7. 发明授权

US08195916B2 Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode 失效
标题翻译：将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法
公开(公告)号：US08195916B2
公开(公告)日：2012-06-05
申请号：US12397438
申请日：2009-03-04
申请人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
发明人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译：公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。

8. 发明申请

US20120110367A1 Architecture and Method for Eliminating Store Buffers in a DSP/Processor with Multiple Memory Accesses 有权
标题翻译：用于消除具有多个存储器访问的DSP /处理器中的存储缓冲器的架构和方法
公开(公告)号：US20120110367A1
公开(公告)日：2012-05-03
申请号：US12916661
申请日：2010-11-01
申请人： Jentsung Ken Lin , Ajay Anant Ingle , Eai-hsin A. Kuo , Paul Douglas Bassett
发明人： Jentsung Ken Lin , Ajay Anant Ingle , Eai-hsin A. Kuo , Paul Douglas Bassett
IPC分类号： G06F1/04 , G06F9/34 , G06F12/00 , G06F12/08 , G06F9/44
CPC分类号： G06F9/3853 , G06F9/30043 , G06F9/3857
摘要： A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions.
摘要翻译：一种用于控制对存储器的系统访问的方法和装置，包括接收第一和第二指令，以及评估两种指令是否可以在架构上完成。当至少一个指令不能在架构上完成时，延迟两个指令。当两个指令都可以在架构上完成并且至少一个是写指令时，调整存储器的写入控制以考虑评估延迟。评估延迟足以评估两种指令是否可以在架构上完成。评估延迟可以输入到写入控制，而不是存储器的读取控制。可以调整存储器的预充电时钟以考虑评估延迟。评估两种指令是否可以在架构上完成可以包括确定每个指令的数据是否位于高速缓存中，以及指令是否是存储器访问指令。

9. 发明申请

US20110193609A1 Voltage Level Shifter with Dynamic Circuit Structure having Discharge Delay Tracking 失效
标题翻译：具有放电延迟跟踪的动态电路结构的电压电平移位器
公开(公告)号：US20110193609A1
公开(公告)日：2011-08-11
申请号：US13047331
申请日：2011-03-14
申请人： Jentsung Lin , Paul Douglas Bassett
发明人： Jentsung Lin , Paul Douglas Bassett
IPC分类号： H03L5/00 , H03K17/28 , H03K17/296
CPC分类号： H03K19/018521 , H03K19/01728 , H03K19/01855 , H03K19/0963
摘要： In a particular embodiment, an apparatus includes a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit.
摘要翻译：在具体实施例中，一种装置包括动态电路结构，其包括耦合预充电电路的动态节点，放电电路和门控保持器电路。门控保护器电路由来自放电延迟跟踪电路的信号使能。

10. 发明授权

US08527804B2 Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accesses 有权
标题翻译：用于消除具有多个存储器访问的DSP /处理器中的存储缓冲器的架构和方法
公开(公告)号：US08527804B2
公开(公告)日：2013-09-03
申请号：US12916661
申请日：2010-11-01
申请人： Jentsung Ken Lin , Ajay Anant Ingle , Eai-hsin A. Kuo , Paul Douglas Bassett
发明人： Jentsung Ken Lin , Ajay Anant Ingle , Eai-hsin A. Kuo , Paul Douglas Bassett
IPC分类号： G06F5/06 , G06F13/00
CPC分类号： G06F9/3853 , G06F9/30043 , G06F9/3857
摘要： A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions.
摘要翻译：一种用于控制对存储器的系统访问的方法和装置，包括接收第一和第二指令，以及评估两种指令是否可以在架构上完成。当至少一个指令不能在架构上完成时，延迟两个指令。当两个指令都可以在架构上完成并且至少一个是写指令时，调整存储器的写入控制以考虑评估延迟。评估延迟足以评估两种指令是否可以在架构上完成。评估延迟可以输入到写入控制，而不是存储器的读取控制。可以调整存储器的预充电时钟以考虑评估延迟。评估两种指令是否可以在架构上完成可以包括确定每个指令的数据是否位于高速缓存中，以及指令是否是存储器访问指令。

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