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1. 发明申请

US20100124101A1 PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE 审中-公开
标题翻译：相变随机访问存储器件
公开(公告)号：US20100124101A1
公开(公告)日：2010-05-20
申请号：US12499894
申请日：2009-07-09
申请人： Mu-hui Park , Soo-guil Yang , Kwang-ho Kim
发明人： Mu-hui Park , Soo-guil Yang , Kwang-ho Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/004 , G11C7/08 , G11C13/00 , G11C13/0004 , G11C2013/0054
摘要： Provided is a phase-change random access memory device. The phase-change random access memory device includes a phase-change memory cell array having multiple phase-change memory cells, a sensing unit and a discharge unit. The sensing unit detects data, stored in a phase-change memory cell to be sensed of the multiple phase-change memory cells, during a sensing period. The discharge unit discharges at least one node of multiple nodes positioned on a sensing path between the phase-change memory cell array and the sensing unit during a period other than the sensing period.
摘要翻译：提供了相变随机存取存储器件。相变随机存取存储装置包括具有多个相变存储单元的相变存储单元阵列，感测单元和放电单元。感测单元在感测周期期间检测存储在要被感测的多个相变存储器单元的相变存储单元中的数据。放电单元在除了感测周期之外的时段期间放电位于相变存储单元阵列和感测单元之间的感测路径上的多个节点的至少一个节点。

2. 发明申请

US20090122593A1 Write driver circuit for phase-change memory, memory including the same, and associated methods 有权
标题翻译：为相变存储器写入驱动电路，包含相同的存储器及相关方法
公开(公告)号：US20090122593A1
公开(公告)日：2009-05-14
申请号：US12292200
申请日：2008-11-13
申请人： Beak-hyung Cho , Kwang-ho Kim , Young-pil Kim
发明人： Beak-hyung Cho , Kwang-ho Kim , Young-pil Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0038 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0069 , G11C2013/0078
摘要： A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit including a write current level adjusting unit configured to determine first to n-th SET state current levels in response to a SET state current level signal, where n is an integer greater than 1, and configured to determine a RESET state current level in response to a RESET state current level signal, and a write current output unit configured to generate one of a SET state current pulse and a RESET state current pulse corresponding to a SET state current level or a RESET state current level determined by the write current level adjusting unit.
摘要翻译：一种用于存储器的写入驱动器电路，其包括响应于所施加的电流脉冲而在RESET状态电阻和SET状态电阻之间改变的相变存储器单元，所述写入驱动器电路包括写入电平电平调整单元，其被配置为从第一至第n 响应于SET状态电流电平信号，其中n是大于1的整数，并且被配置为响应于RESET状态电流信号确定RESET状态电流电平，并且写入电流输出单元被配置为产生与由写入电平电平调整单元确定的SET状态电流电平或RESET状态电流电平对应的SET状态电流脉冲和RESET状态电流脉冲之一。

3. 发明授权

US08023320B2 Resistance-change random access memory device including memory cells connected to discharge elements 有权
标题翻译：电阻变化随机存取存储器件包括连接到放电元件的存储单元
公开(公告)号：US08023320B2
公开(公告)日：2011-09-20
申请号：US12591238
申请日：2009-11-13
申请人： Hye-jin Kim , Kwang-ho Kim , Young-kug Moon , Byung-gil Choi
发明人： Hye-jin Kim , Kwang-ho Kim , Young-kug Moon , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C7/12 , G11C8/12 , G11C13/00 , G11C13/0004 , G11C13/0026 , G11C13/0028
摘要： A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.
摘要翻译：电阻变化随机存取存储器件包括具有多个电阻变化存储单元的电阻变化存储单元阵列，其中多个字线连接到多个电阻变化存储单元的相应第一端子。多个位线垂直于字线布置并连接到多个电阻变化存储单元的相应的第二端子。该装置还包括能够将各个位线与放电电压连接或断开的多个放电元件，其中放电元件在写入和读取操作之前将各个位线连接到放电电压。

4. 发明申请

US20110002169A1 Bad Column Management with Bit Information in Non-Volatile Memory Systems 审中-公开
标题翻译：在非易失性存储器系统中具有位信息的错误列管理
公开(公告)号：US20110002169A1
公开(公告)日：2011-01-06
申请号：US12498220
申请日：2009-07-06
申请人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
发明人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
IPC分类号： G11C16/06 , G11C29/00 , G11C7/10 , G11C16/04
CPC分类号： G11C29/00 , G11C16/10 , G11C29/808
摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area.
摘要翻译：介绍了基于列的缺陷管理技术。存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，还使用附加信息来指示是否要对列进行整体处理作为缺陷，或者列的单个位是否有缺陷。然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。当列是坏的但是仅在位电平时，好的位仍然可以用于数据，尽管这可以在对于某些位的编程的惩罚下完成，如下面进一步描述的。还描述了通过一组列测试来构建的用于收集位信息的自建内置自检（BIST）流程。基于该信息，可以通过控制器或存储器提取坏位并将其重新分组为字节，以更有效地使用列冗余区域。

5. 发明授权

US07711340B2 Phase locked loop and method thereof 有权
标题翻译：锁相环及其方法
公开(公告)号：US07711340B2
公开(公告)日：2010-05-04
申请号：US11656472
申请日：2007-01-23
申请人： Kwang-ho Kim , Je-kook Kim
发明人： Kwang-ho Kim , Je-kook Kim
IPC分类号： H04B1/06 , H04Q7/20
CPC分类号： H03L7/099 , H03L7/0891 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： A phase locked loop and method thereof are provided. The example phase locked loop may include a loop filter filtering a charge pump output signal to generate a voltage signal and a voltage-controlled oscillator configured to operate in a given one of a plurality of frequency zones, the given frequency zone within which the voltage-controller oscillator is operating in being based on a voltage level of the voltage signal, the voltage-controlled oscillator outputting an oscillator signal at a frequency corresponding to the voltage level of the voltage signal output from the loop filter. The example method may include filtering a charge pump output signal to generate a voltage signal and outputting an oscillator signal at a frequency corresponding to a voltage level of the voltage signal, the frequency of the oscillator signal based on which of a plurality of frequency zones is currently selected, the currently selected frequency zone being selected based on the voltage level of the voltage signal.
摘要翻译：提供了一种锁相环及其方法。示例性锁相环可以包括滤波电荷泵输出信号以产生电压信号的环路滤波器，以及被配置为在多个频率区域中给定的一个频率区域中工作的压控振荡器，该给定频率区域中的电压 - 控制振荡器基于电压信号的电压电平工作，压控振荡器以与从环路滤波器输出的电压信号的电压电平相对应的频率输出振荡器信号。示例性方法可以包括过滤电荷泵输出信号以产生电压信号，并以与电压信号的电压电平对应的频率输出振荡器信号，基于多个频率区域中的哪个频率区域的振荡器信号的频率当前选择的，当前选择的频率区域是基于电压信号的电压电平被选择的。

6. 发明申请

US20100309720A1 Structure and Method for Shuffling Data Within Non-Volatile Memory Devices 有权
标题翻译：在非易失性存储器件中进行数据混合的结构和方法
公开(公告)号：US20100309720A1
公开(公告)日：2010-12-09
申请号：US12635449
申请日：2009-12-10
申请人： Bo Liu , Yan Li , Alexander Kwok-Tung Mak , Chi-Ming Wang , Eugene Jinglun Tam , Kwang-ho Kim
发明人： Bo Liu , Yan Li , Alexander Kwok-Tung Mak , Chi-Ming Wang , Eugene Jinglun Tam , Kwang-ho Kim
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/34 , G11C2211/5641 , G11C2211/5642
摘要： Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.
摘要翻译：描述用于在多状态非易失性存储器中读取和写入数据的技术。数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。还描述了数据“展开”的相应的读取技术。这些技术进一步允许在控制器上用纠错码（ECC）编码数据，该数据在将数据传送到存储器以二进制形式写入之前考虑到其最终的多状态存储。还提出了允许这种“折叠”操作的寄存器结构。一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

7. 发明授权

US07817489B2 Power supplying circuit and phase-change random access memory including the same 有权
标题翻译：供电电路和包括相同的相变随机存取存储器
公开(公告)号：US07817489B2
公开(公告)日：2010-10-19
申请号：US12251761
申请日：2008-10-15
申请人： Beak-hyung Cho , Kwang-ho Kim , Won-seok Lee
发明人： Beak-hyung Cho , Kwang-ho Kim , Won-seok Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C13/0004 , G11C13/0038
摘要： A power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured to output a second voltage to a second terminal, the second voltage generator including: a voltage pump unit configured to output the second voltage based on a clock signal and a pump control signal; a pump output detector coupled to the voltage pump unit, the pump output detector configured to output a pump output detection signal; and a discharging unit coupled to the voltage pump unit, the discharging unit configured to discharge a level of the second voltage to a predetermined level in response to a discharge signal. Embodiments of the invention may prevent write and/or read malfunctions that can occur due to changes in the level of a voltage supplied to PRAM cell blocks.
摘要翻译：供电电路（PSC）和包括PSC的相变随机存取存储器（PRAM）。根据本发明的一个方面，PSC包括：第一电压发生器，被配置为将第一电压输出到第一端子; 以及第二电压发生器，被配置为向第二端子输出第二电压，所述第二电压发生器包括：电压泵单元，被配置为基于时钟信号和泵控制信号输出所述第二电压; 耦合到所述电压泵单元的泵输出检测器，所述泵输出检测器被配置为输出泵输出检测信号; 以及耦合到所述电压泵单元的放电单元，所述放电单元被配置为响应于放电信号将所述第二电压的电平放电到预定电平。本发明的实施例可以防止由于提供给PRAM单元块的电压的电平的变化而可能发生的写入和/或读取故障。

8. 发明申请

US20100125716A1 RESISTANCE VARIABLE MEMORY DEVICE 有权
标题翻译：电阻可变存储器件
公开(公告)号：US20100125716A1
公开(公告)日：2010-05-20
申请号：US12617758
申请日：2009-11-13
申请人： Kwang-jin Lee , Young-kug Moon , Kwang-ho Kim
发明人： Kwang-jin Lee , Young-kug Moon , Kwang-ho Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/0215 , G06F12/0238 , G06F2212/7203 , G11C7/103 , G11C13/0004 , G11C13/004 , Y02D10/13
摘要： A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received
摘要翻译：电阻可变存储器件包括电阻可变存储单元阵列，预取电阻可变存储单元阵列的读取数据的数据寄存器，从数据寄存器接收预取的读取数据并输出接收的数据的数据输出单元，以及页面模式设置单元，其将第一页面模式和第二页面模式之一设置为页面模式。在第一页面模式中，数据输出单元顺序地读取在数据寄存器中预取的读取数据，因为顺序地接收页面地址，而在第二页面模式中，数据输出单元顺序地读取在数据寄存器中预读取的读取数据已经接收到多个页地址中的起始页地址

9. 发明申请

US20090251953A1 Variable resistance memory device 有权
标题翻译：可变电阻存储器件
公开(公告)号：US20090251953A1
公开(公告)日：2009-10-08
申请号：US12314965
申请日：2008-12-19
申请人： Byung-gil Choi , Kwang-ho Kim
发明人： Byung-gil Choi , Kwang-ho Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0023 , G11C8/08 , G11C8/14 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C2213/72
摘要： A variable resistance memory device includes a variable resistance memory cell array including a plurality of variable resistance memory cells; a plurality of global word lines configured to drive the variable resistance memory cell array; and a plurality of local word line decoders. Each of the plurality of local word line decoders includes a first transistor having a gate connected to the global word line. A voltage greater than an operation voltage of one or more of the plurality of local word line decoders is applied to a selected one of the plurality of global word lines.
摘要翻译：可变电阻存储器件包括：包括多个可变电阻存储单元的可变电阻存储单元阵列; 配置成驱动可变电阻存储单元阵列的多个全局字线; 和多个本地字线解码器。多个本地字线解码器中的每一个包括具有连接到全局字线的栅极的第一晶体管。大于多个本地字线解码器中的一个或多个的操作电压的电压被施加到多个全局字线中的所选择的一个。

10. 发明申请

US20090235036A1 PHASE-CHANGE RANDOM ACCESS MEMORY AND METHOD OF SETTING BOOT BLOCK THEREIN 有权
标题翻译：相变随机访问存储器和设置引导块的方法
公开(公告)号：US20090235036A1
公开(公告)日：2009-09-17
申请号：US12402006
申请日：2009-03-11
申请人： Yu-hwan RO , Kwang-ho Kim , Kwang-jin Lee , Joon-yong Choi
发明人： Yu-hwan RO , Kwang-ho Kim , Kwang-jin Lee , Joon-yong Choi
IPC分类号： G06F12/16 , G06F12/00 , G06F12/02
CPC分类号： G06F12/0238 , G06F12/0223 , Y02D10/13
摘要： A semiconductor memory device includes a memory cell array and the memory cell array includes: a plurality of memory blocks and at least one setting unit. The at least one setting unit stores a location and a size of a boot data storage region within the plurality of memory blocks that stores boot data. The at least one setting units may include a register for setting usage of each memory block as a boot block. The semiconductor device may be a phase-change memory.
摘要翻译：半导体存储器件包括存储单元阵列，存储单元阵列包括：多个存储块和至少一个设置单元。所述至少一个设置单元将存储引导数据的多个存储块内的引导数据存储区域的位置和大小存储起来。至少一个设置单元可以包括用于将每个存储器块的使用设置为引导块的寄存器。半导体器件可以是相变存储器。

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