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1. 发明授权

US08704570B2 Delay-locked loop with phase adjustment 有权
标题翻译：延时锁相环调相
公开(公告)号：US08704570B2
公开(公告)日：2014-04-22
申请号：US13720981
申请日：2012-12-19
申请人： Aldo Bottelli , Prashant Choudhary , Charles W Boecker
发明人： Aldo Bottelli , Prashant Choudhary , Charles W Boecker
IPC分类号： H03L7/06
CPC分类号： H03L1/00 , H03L7/07 , H03L7/08 , H03L7/0816 , H04L7/0338
摘要： A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
摘要翻译：延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

2. 发明授权

US07996736B2 Bad page marking strategy for fast readout in memory 有权
标题翻译：内存中快速读取的不良页面标记策略
公开(公告)号：US07996736B2
公开(公告)日：2011-08-09
申请号：US12400091
申请日：2009-03-09
申请人： Aldo Bottelli , Luca Fasoli
发明人： Aldo Bottelli , Luca Fasoli
IPC分类号： G11C29/00 , G06F13/00 , G06F9/26
CPC分类号： G11C29/812 , G11C29/802 , G11C29/82
摘要： A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit.
摘要翻译：用于识别存储设备中的存储元件的不良页面的技术。为一个或多个页面的每个页面组提供标志字节，其指示页面组是否正常。根据标志字节中的位位置，所选页组的标志字节还指示较大的页组是否健康。坏页识别过程包括以选定的粒度读取标志字节，以便不读取所有标志字节。可选地，当将更大的页组组识别为具有至少一个坏页时，下钻过程读取较小组页组的标志字节。这允许识别坏页组并且标记更加特异性。标志字节的冗余副本可以存储在存储设备的不同位置。多数投票过程为每个位分配一个值。

3. 发明授权

US07966532B2 Method for selectively retrieving column redundancy data in memory device 有权
标题翻译：用于选择性地检索存储器设备中的列冗余数据的方法
公开(公告)号：US07966532B2
公开(公告)日：2011-06-21
申请号：US12414935
申请日：2009-03-31
申请人： Aldo Bottelli , Luca Fasoli , Doug Sojourner
发明人： Aldo Bottelli , Luca Fasoli , Doug Sojourner
IPC分类号： G11C29/00
CPC分类号： G11C29/812 , G11C29/802 , G11C29/82
摘要： Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials.
摘要翻译：根据当前正在被访问的一组存储元件，例如在读取或写入操作中，在存储器件中选择性地检索列冗余数据。存储器设备被组织成诸如逻辑块的存储元件组，其中列冗余数据从非易失性存储位置加载到正被访问的一个或多个特定块的易失性存储位置。易失性存储位置仅需要足够大以存储当前数据条目。可以基于期望的最大缺陷数量和期望的修复概率来配置列冗余数据同时加载的存储元件组的大小。在制造生命周期中，随着制造工艺和材料的改进，缺陷数量的减少可以增加组件的尺寸。

4. 发明申请

US20130154698A1 DELAY-LOCKED LOOP WITH PHASE ADJUSTMENT 有权
标题翻译：延迟锁定环路进行相位调整
公开(公告)号：US20130154698A1
公开(公告)日：2013-06-20
申请号：US13720981
申请日：2012-12-19
申请人： Aldo Bottelli , Prashant Choudhary , Charles W. Boecker
发明人： Aldo Bottelli , Prashant Choudhary , Charles W. Boecker
IPC分类号： H03L7/07
CPC分类号： H03L1/00 , H03L7/07 , H03L7/08 , H03L7/0816 , H04L7/0338
摘要： A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
摘要翻译：延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

5. 发明申请

US20110002169A1 Bad Column Management with Bit Information in Non-Volatile Memory Systems 审中-公开
标题翻译：在非易失性存储器系统中具有位信息的错误列管理
公开(公告)号：US20110002169A1
公开(公告)日：2011-01-06
申请号：US12498220
申请日：2009-07-06
申请人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
发明人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
IPC分类号： G11C16/06 , G11C29/00 , G11C7/10 , G11C16/04
CPC分类号： G11C29/00 , G11C16/10 , G11C29/808
摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area.
摘要翻译：介绍了基于列的缺陷管理技术。存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，还使用附加信息来指示是否要对列进行整体处理作为缺陷，或者列的单个位是否有缺陷。然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。当列是坏的但是仅在位电平时，好的位仍然可以用于数据，尽管这可以在对于某些位的编程的惩罚下完成，如下面进一步描述的。还描述了通过一组列测试来构建的用于收集位信息的自建内置自检（BIST）流程。基于该信息，可以通过控制器或存储器提取坏位并将其重新分组为字节，以更有效地使用列冗余区域。

6. 发明申请

US20100107022A1 BAD PAGE MARKING STRATEGY FOR FAST READOUT IN MEMORY 有权
标题翻译：用于快速读取内存中的BAD PAGE标记策略
公开(公告)号：US20100107022A1
公开(公告)日：2010-04-29
申请号：US12400091
申请日：2009-03-09
申请人： Aldo Bottelli , Luca Fasoli
发明人： Aldo Bottelli , Luca Fasoli
IPC分类号： G06F12/00 , G11C29/08 , G06F11/26
CPC分类号： G11C29/812 , G11C29/802 , G11C29/82
摘要： A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit.
摘要翻译：用于识别存储设备中的存储元件的不良页面的技术。为一个或多个页面的每个页面组提供标志字节，其指示页面组是否正常。根据标志字节中的位位置，所选页组的标志字节还指示较大的页组是否健康。坏页识别过程包括以选定的粒度读取标志字节，以便不读取所有标志字节。可选地，当将更大的页组组识别为具有至少一个坏页时，下钻过程读取较小组页组的标志字节。这允许识别坏页组并且标记更加特异性。标志字节的冗余副本可以存储在存储设备的不同位置。多数投票过程为每个位分配一个值。

7. 发明授权

US08711625B2 Bad column management with bit information in non-volatile memory systems 有权
标题翻译：在非易失性存储器系统中使用位信息进行不良列管理
公开(公告)号：US08711625B2
公开(公告)日：2014-04-29
申请号：US13293494
申请日：2011-11-10
申请人： Yan Li , Kwang-Ho Kim , Frank W. Tsai , Aldo Bottelli
发明人： Yan Li , Kwang-Ho Kim , Frank W. Tsai , Aldo Bottelli
IPC分类号： G11C16/06
CPC分类号： G11C29/00 , G11C16/10 , G11C29/808
摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data.
摘要翻译：介绍了基于列的缺陷管理技术。存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示该列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，还使用附加信息来指示该列是作为一个整体进行处理作为缺陷，或者列的单个位是否有缺陷。然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。当列是坏的，但是仅在位级别，好的位仍然可以用于数据。

8. 发明申请

US20120297245A1 Bad Column Management with Bit Information in Non-Volatile Memory Systems 有权
标题翻译：在非易失性存储器系统中具有位信息的错误列管理
公开(公告)号：US20120297245A1
公开(公告)日：2012-11-22
申请号：US13293494
申请日：2011-11-10
申请人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
发明人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
IPC分类号： G06F11/07 , H03M13/05
CPC分类号： G11C29/00 , G11C16/10 , G11C29/808
摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data.
摘要翻译：介绍了基于列的缺陷管理技术。存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，还使用附加信息来指示是否要对列进行整体处理作为缺陷，或者列的单个位是否有缺陷。然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。当列是坏的，但是仅在位级别，好的位仍然可以用于数据。

9. 发明申请

US20100107004A1 METHOD FOR SELECTIVELY RETRIEVING COLUMN REDUNDANCY DATA IN MEMORY DEVICE 有权
标题翻译：用于选择性地在存储器件中检索色谱冗余数据的方法
公开(公告)号：US20100107004A1
公开(公告)日：2010-04-29
申请号：US12414935
申请日：2009-03-31
申请人： Aldo Bottelli , Luca Fasoli , Doug Sojourner
发明人： Aldo Bottelli , Luca Fasoli , Doug Sojourner
IPC分类号： G06F11/20 , G06F12/00 , G06F12/16 , G06F12/02
CPC分类号： G11C29/812 , G11C29/802 , G11C29/82
摘要： Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials.
摘要翻译：根据当前正在被访问的一组存储元件，例如在读取或写入操作中，在存储器件中选择性地检索列冗余数据。存储器设备被组织成诸如逻辑块的存储元件组，其中列冗余数据从非易失性存储位置加载到正被访问的一个或多个特定块的易失性存储位置。易失性存储位置仅需要足够大以存储当前数据条目。可以基于期望的最大缺陷数量和期望的修复概率来配置列冗余数据同时加载的存储元件组的大小。在制造生命周期中，随着制造工艺和材料的改进，缺陷数量的减少可以增加组件的尺寸。

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