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1. 发明授权

US09547360B2 Systems having a maximum sleep mode and method of operating the same 有权
标题翻译：具有最大睡眠模式的系统及其操作方法
公开(公告)号：US09547360B2
公开(公告)日：2017-01-17
申请号：US14091912
申请日：2013-11-27
申请人： Young-Jin Park , Won-Seok Lee , Il-Guy Jung
发明人： Young-Jin Park , Won-Seok Lee , Il-Guy Jung
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3209 , G06F1/3225 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A main memory system includes a main memory device including a first memory device implemented with a volatile memory and a second memory device implemented with a non-volatile memory, the main memory system being configured such that, when entering a sleep mode, the memory device reads a portion of data stored in the first memory device to store the read data in the second memory device, and, after the portion of data is read, the first memory device and the second memory device are powered off.
摘要翻译：主存储器系统包括主存储器件，其包括实施有易失性存储器的第一存储器件和由非易失性存储器实现的第二存储器件，所述主存储器系统被配置为使得当进入休眠模式时，存储器件读取存储在第一存储器件中的数据的一部分以将读取的数据存储在第二存储器件中，并且在数据的部分被读取之后，第一存储器件和第二存储器件被断电。

2. 发明授权

US09470548B2 Device, system and method for calibration of camera and laser sensor 有权
标题翻译：用于相机和激光传感器校准的装置，系统和方法
公开(公告)号：US09470548B2
公开(公告)日：2016-10-18
申请号：US13949622
申请日：2013-07-24
申请人： Seong Yong Ahn , Tok Son Choe , Yong Woon Park , Won Seok Lee
发明人： Seong Yong Ahn , Tok Son Choe , Yong Woon Park , Won Seok Lee
IPC分类号： G01C23/00 , G01S7/497 , G01S17/08 , G01S17/87
CPC分类号： G01C23/00 , G01S7/497 , G01S17/08 , G01S17/87
摘要： Disclosed are a calibration device, a calibration system and a calibration method. The calibration device includes a camera configured to capture image information, a laser sensor configured to capture image information, a laser sensor configured to detect distance information, and a calibration module configured to perform a calibration of the camera and the laser sensor by obtaining a relation between the image information and the distance information, wherein the calibration module includes a plane member disposed to intersect a scanning surface of the laser sensor such that an intersection line is generated, and disposed within a capturing range by the camera so as to be captured by the camera, and a controller configured to perform coordinate conversions with respect to the image information and the distance information based on a ratio between one side of the plane member and the intersection line, and based on a plane member image included in the image information. Under these configurations, a calibration is performed through direct coordinate conversions with respect to image information and distance information.
摘要翻译：公开了一种校准装置，校准系统和校准方法。该校准装置包括被配置为捕获图像信息的相机，被配置为捕获图像信息的激光传感器，被配置为检测距离信息的激光传感器，以及被配置为通过获得关系来执行相机和激光传感器的校准的校准模块在所述图像信息和所述距离信息之间，其中所述校准模块包括布置成与所述激光传感器的扫描表面相交的平面构件，使得生成交叉线，并且通过所述相机设置在捕获范围内，以被所述摄像机捕获相机和配置为基于平面构件的一侧与交叉线之间的比率，并且基于包括在图像信息中的平面构件图像来执行关于图像信息和距离信息的坐标转换的控制器。在这些配置下，通过对图像信息和距离信息的直接坐标转换执行校准。

3. 发明授权

US08780656B2 Stacked memory device and method of repairing same 失效
标题翻译：堆叠式存储器件及其修复方法
公开(公告)号：US08780656B2
公开(公告)日：2014-07-15
申请号：US13015847
申请日：2011-01-28
申请人： Chul-Woo Park , Hong-Sun Hwang , Sang-Beom Kang , Won-Seok Lee
发明人： Chul-Woo Park , Hong-Sun Hwang , Sang-Beom Kang , Won-Seok Lee
IPC分类号： G11C7/00 , G11C5/02
CPC分类号： G11C5/025 , G11C29/80
摘要： A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield.
摘要翻译：层叠的半导体存储器件包括以倒置的楔形堆叠并且具有彼此不同的冗余尺寸的存储单元阵列层。层叠的半导体存储器件具有用于层之间的垂直连接的空间，相对较小的尺寸和相对较高的产量。

4. 发明申请

US20130318358A1 APPARATUS FOR GENERATING SECURE KEY USING DEVICE AND USER AUTHENTICATION INFORMATION 有权
标题翻译：用于使用设备产生安全密钥的设备和用户认证信息
公开(公告)号：US20130318358A1
公开(公告)日：2013-11-28
申请号：US13798475
申请日：2013-03-13
申请人： Weixin Wang , Hee-Chang Cho , Won-Seok Lee , Min-Wook Kim , Hyoung-Suk Jang
发明人： Weixin Wang , Hee-Chang Cho , Won-Seok Lee , Min-Wook Kim , Hyoung-Suk Jang
IPC分类号： G06F21/31
CPC分类号： G06F21/31 , G06F21/57 , G06F2221/2105 , G06F2221/2107 , H04L9/0866
摘要： A secure key generating apparatus comprising an ID calculating unit receiving a primitive ID from a first storage device and calculating a first media ID, (a unique identifier of the first storage device), from the first primitive ID; a user authentication information providing unit providing user authentication information for authenticating the current; and a secure key generating unit for generating a first Secure Key using both the first media ID and the first user's authentication information. The Secure Key is used to encrypt/decrypt content stored in the first storage device. The secure key generating unit generates a first different Secure Key using a second media ID of a second storage device, and generates a second different Secure Key using second user's user authentication information. Only the first Secure Key can be used to decrypt encrypted content stored in the first storage device that was encrypted using the first Secure Key.
摘要翻译：一种安全密钥生成装置，包括ID计算单元，从第一存储装置接收原始ID，并从第一基元ID计算第一媒体ID（第一存储装置的唯一标识符）; 用户认证信息提供单元提供用于认证当前的用户认证信息; 以及安全密钥生成单元，用于使用第一媒体ID和第一用户的认证信息来生成第一安全密钥。安全密钥用于加密/解密存储在第一存储设备中的内容。安全密钥生成单元使用第二存储设备的第二媒体ID生成第一不同的安全密钥，并且使用第二用户的用户认证信息生成第二不同的安全密钥。只有第一个安全密钥可用于解密使用第一个安全密钥加密的第一个存储设备中存储的加密内容。

5. 发明申请

US20130166410A1 PAYMENT AGENCY SYSTEM, USER TERMINAL AND MARKET SERVER 审中-公开
标题翻译：付款代理系统，用户终端和市场服务器
公开(公告)号：US20130166410A1
公开(公告)日：2013-06-27
申请号：US13486570
申请日：2012-06-01
申请人： Won-Seok LEE
发明人： Won-Seok LEE
IPC分类号： G06Q30/06
CPC分类号： G06Q30/06
摘要： A payment agency system, a user terminal, and a market server are provided. The payment agency system includes an issue unit that generates at least one payment ticket according to a request of a user terminal and that transmits the at least one payment ticket to the user terminal; and an accounting processor that receives purchase information and a payment ticket of pay digital contents in which the user terminal purchases from a market server and that performs an accounting processing of the pay digital contents using the payment ticket and the purchase information.
摘要翻译：提供支付代理系统，用户终端和市场服务器。支付代理系统包括：发行单元，其根据用户终端的请求生成至少一个支付单，并将该至少一个支付单发送给用户终端; 以及会计处理器，其接收购买信息和用户终端从市场服务器购买的付费数字内容的支付票，并且使用支付票和购买信息执行付费数字内容的会计处理。

6. 发明申请

US20110209030A1 SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME 有权
标题翻译：半导体存储器件及其数据错误检测及校正方法
公开(公告)号：US20110209030A1
公开(公告)日：2011-08-25
申请号：US13099640
申请日：2011-05-03
申请人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
发明人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1008 , G06F11/1076 , G11C8/04 , G11C8/12
摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.
摘要翻译：半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为检测并输出校正的读取数据。

7. 发明授权

US07580278B2 Variable resistance memory device 有权
标题翻译：可变电阻存储器件
公开(公告)号：US07580278B2
公开(公告)日：2009-08-25
申请号：US11868992
申请日：2007-10-09
申请人： Beak-Hyung Cho , Jong-Soo Seo , Won-Seok Lee
发明人： Beak-Hyung Cho , Jong-Soo Seo , Won-Seok Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72 , G11C2213/79
摘要： A variable resistance memory device includes a memory cell array having a plurality of memory cells, a write driver which supplies a step-down set current to the memory cells, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver. The set program control circuit controls the duration of the step-down set current in accordance with at least one of data contained in an mode register set (MRS) and a conductive state of a fuse element.
摘要翻译：可变电阻存储器件包括具有多个存储器单元的存储单元阵列，一个写入驱动器，其将降压设定电流提供给存储器单元，其中降压设定电流包括多个连续的步骤，其降低电流幅度以及控制由写入驱动器提供的降压设定电流的持续时间的设定程序控制电路。设定程序控制电路根据包含在模式寄存器组（MRS）和熔丝元件的导通状态中的至少一个数据来控制降压设定电流的持续时间。

8. 发明授权

US07535760B2 Memory devices and memory systems having the same 有权
标题翻译：具有相同的存储器件和存储器系统
公开(公告)号：US07535760B2
公开(公告)日：2009-05-19
申请号：US11902424
申请日：2007-09-21
申请人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
发明人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
IPC分类号： G11C14/00
CPC分类号： H01L27/10802 , G11C7/00 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/1084 , G11C11/4063 , H01L21/84 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.
摘要翻译：公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。

9. 发明申请

US20080112220A1 Input circuit of a non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件的输入电路
公开(公告)号：US20080112220A1
公开(公告)日：2008-05-15
申请号：US11984145
申请日：2007-11-14
申请人： Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
发明人： Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/225 , G11C16/10
摘要： A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.
摘要翻译：非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

10. 发明申请

US20050082548A1 III-V group GaN-based semiconductor device and method of manufacturing the same 审中-公开
标题翻译： III-V族GaN基半导体器件及其制造方法
公开(公告)号：US20050082548A1
公开(公告)日：2005-04-21
申请号：US10951905
申请日：2004-09-29
申请人： Tan Sakong , Ho-sun Paek , Sung-nam Lee , Joong-kon Son , Won-seok Lee
发明人： Tan Sakong , Ho-sun Paek , Sung-nam Lee , Joong-kon Son , Won-seok Lee
IPC分类号： B82Y20/00 , H01S5/02 , H01S5/20 , H01S5/343 , H01L21/00 , H01L27/15 , H01L29/26 , H01L31/12 , H01L33/00
CPC分类号： B82Y20/00 , H01S5/02 , H01S5/2009 , H01S5/3072 , H01S5/34333 , H01S2301/173 , H01S2301/176 , H01S2304/00
摘要： Provided are a III-V group GaN-based compound semiconductor device and a method of manufacturing the same. The device includes an AlGaN diffusion blocking layer and an InGaN sacrificial layer interposed between an active layer having a multiple quantum well and a p-type GaN-based compound semiconductor layer.
摘要翻译：提供III-V族GaN基化合物半导体器件及其制造方法。该器件包括插入在具有多量子阱的有源层和p型GaN基化合物半导体层之间的AlGaN扩散阻挡层和InGaN牺牲层。

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