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1. 发明授权

US06521671B1 Micelle dispersion and method for preparation thereof 失效
标题翻译：胶束分散体及其制备方法
公开(公告)号：US06521671B1
公开(公告)日：2003-02-18
申请号：US09673663
申请日：2000-11-06
申请人： Motoharu Ishikawa , Hideaki Kurata
发明人： Motoharu Ishikawa , Hideaki Kurata
IPC分类号： B01F1700
CPC分类号： C25D15/00 , G02B5/201 , G02B5/223
摘要： A micelle dispersion containing hydrophobic particles, conductive particles and a surfactant of a ferrocene derivative dispersed in an aqueous medium. The surfactant of a ferrocene derivative in an equilibrium concentration contains an oxidized compound in a concentration of 40 &mgr;g/ml or less and a reduced compound in a concentration of 50 to 300 &mgr;g/ml. A process for producing a micelle dispersion including dispersing hydrophobic particles, conductive particles and a surfactant of a ferrocene derivative in an aqueous medium, where an oxidized compound in the surfactant of a ferrocene derivative is removed with at least one of an ion exchange resin and a reducing agent. A color filter can be produced in excellent yield without color overlapping by using the micelle dispersion and the process provides the micelle dispersion.
摘要翻译：含有分散在水介质中的疏水性颗粒，导电颗粒和二茂铁衍生物的表面活性剂的胶束分散体。平衡浓度的二茂铁衍生物的表面活性剂含有浓度为40mug / ml以下的氧化化合物，浓度为50〜300mug / ml的还原化合物。一种制备胶束分散体的方法，包括将疏水性颗粒，导电颗粒和二茂铁衍生物的表面活性剂分散在水性介质中，其中二茂铁衍生物的表面活性剂中的氧化化合物用离子交换树脂和还原剂。通过使用胶束分散体，可以以优异的产率制造无色重叠的滤色器，并且该方法提供胶束分散体。

2. 发明授权

US09037448B2 Computer system, program, and method for assigning computational resource to be used in simulation 有权
标题翻译：用于分配计算资源的计算机系统，程序和方法用于仿真
公开(公告)号：US09037448B2
公开(公告)日：2015-05-19
申请号：US13387243
申请日：2010-07-16
申请人： Yasuhiro Ito , Yasuo Sugure , Shigeru Oho , Hideaki Kurata
发明人： Yasuhiro Ito , Yasuo Sugure , Shigeru Oho , Hideaki Kurata
IPC分类号： G06F9/44 , G06F11/36 , G06F9/50
CPC分类号： G06F11/3664 , G06F9/5055
摘要： The cost necessary for introducing and maintaining a development environment that includes multiple simulators is suppressed, and a sharing of designing information is promoted, to make parameter adjustment of simulators easy. Provided is a service that unifies development environment on a computer provided with: a working computer system that can guarantee that there is no leaking of designing files; a user behavior monitoring system that collects utilization history of simulators or software, for each of the users, and selects development process of each of the users from the collected information; and a dynamic computational-resource distribution system that can conduct an automatic optimization of a complex simulation configuration, from information collected by the aforementioned user behavior monitoring system.
摘要翻译：引入和维护包含多个模拟器的开发环境所需的成本被抑制，并且提高了设计信息的共享，从而使模拟器的参数调整变得容易。提供了一种将计算机上的开发环境统一起来的服务，它具有：可以保证设计文件不泄漏的工作计算机系统; 用户行为监控系统，用于为每个用户收集模拟器或软件的利用历史，并从收集的信息中选择每个用户的开发过程; 以及动态计算资源分配系统，可以从上述用户行为监控系统收集的信息中进行复杂模拟配置的自动优化。

3. 发明授权

US07969760B2 Semiconductor memory device and manufacturing method of the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07969760B2
公开(公告)日：2011-06-28
申请号：US11790590
申请日：2007-04-26
申请人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
发明人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
IPC分类号： G11C5/06
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.
摘要翻译：本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。在选择晶体管的栅电极上形成两条选择线。一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。也就是说，在选择线和栅电极之间形成绝缘膜。如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。选择线被构造成连接到另一个选择晶体管。

4. 发明授权

US07366015B2 Semiconductor integrated circuit device, production and operation method thereof 有权
标题翻译：半导体集成电路器件，其生产和操作方法
公开(公告)号：US07366015B2
公开(公告)日：2008-04-29
申请号：US11700085
申请日：2007-01-31
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0425 , G11C16/12 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.
摘要翻译：一种半导体集成器件，具有多个存储单元，每个存储单元包括通过绝缘膜形成在浮置栅极的侧表面上的浮置栅极，控制栅极和辅助栅极。耦合到选择的存储单元的辅助栅极用于产生热电子，并且与其他辅助栅极交替布置，其功能是防止未选择的存储器单元中的写入错误。

5. 发明申请

US20080055983A1 Semiconductor memory device comprising controllable threshold voltage dummy memory cells 审中-公开
标题翻译：半导体存储器件包括可控阈值电压虚拟存储器单元
公开(公告)号：US20080055983A1
公开(公告)日：2008-03-06
申请号：US11976299
申请日：2007-10-23
申请人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
发明人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
IPC分类号： G11C16/28
CPC分类号： G11C8/14
摘要： An object of the present invention is to provide a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block, a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliably operation.
摘要翻译：本发明的目的是提供一种半导体存储器件，其能够防止由于字线的下降引起的缺陷以及由于在存储器块的端部处的字线的间距的干扰而导致的图案精度的劣化。多个虚拟字线设置在存储器块的末端，为虚拟字线安装字驱动器以控制形成在虚拟字线下面的虚拟存储器单元的阈值电压。此外，在操作用于存储来自外部的数据的存储区域时，偏置被施加到虚拟字线。本发明可以防止由于字线下降引起的缺陷和由于记忆块末端的字线的间距的干扰导致的图案精度的劣化，并且实现高产率和可靠的操作。

6. 发明申请

US20070285983A1 Semiconductor memory device and manufacturing method of the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070285983A1
公开(公告)日：2007-12-13
申请号：US11790590
申请日：2007-04-26
申请人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
发明人： Tomoyuki Ishii , Yoshitaka Sasago , Hideaki Kurata , Toshiyuki Mine
IPC分类号： G11C11/34 , H01L21/336
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.
摘要翻译：本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。在选择晶体管的栅电极上形成两条选择线。一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。也就是说，在选择线和栅电极之间形成绝缘膜。如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。选择线被构造成连接到另一个选择晶体管。

7. 发明申请

US20060275986A1 Semiconductor intergrated circuit device and process for producing the same 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20060275986A1
公开(公告)日：2006-12-07
申请号：US11499756
申请日：2006-08-07
申请人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
发明人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7881
摘要： A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.
摘要翻译：具有第三栅极的半导体集成电路器件包括形成在第一导电型阱201的第二导电型源极/漏极扩散层区域205，通过绝缘膜202形成在半导体衬底200上的浮置栅极203b，形成在浮动栅极203上的控制栅极211a b通过氮引入氧化硅膜210a和与通过半导体衬底，浮栅，控制栅极和绝缘膜形成的浮栅和控制栅极不同的第三栅极207a，其中第三栅极形成为填充在垂直方向上存在的浮动栅极与字线和沟道之间的间隙以及如此形成的第三栅极207a的高度低于浮动栅极203b的高度，具有改善的存储单元尺寸和操作速度的降低和改进编程/擦除周期后的可靠性。

8. 发明申请

US20060065920A1 Semiconductor memory device and method for producing the same 有权
公开(公告)号：US20060065920A1
公开(公告)日：2006-03-30
申请号：US11271739
申请日：2005-11-14
申请人： Tomoyuki Ishii , Taro Osabe , Hideaki Kurata , Takeshi Sakata
发明人： Tomoyuki Ishii , Taro Osabe , Hideaki Kurata , Takeshi Sakata
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5621 , G11C11/5671 , G11C16/0433 , G11C16/0458 , G11C16/0475 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521
摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

9. 发明授权

US06813185B2 Non-volatile semiconductor memory device and semiconductor disk device 失效
标题翻译：非易失性半导体存储器件和半导体磁盘器件
公开(公告)号：US06813185B2
公开(公告)日：2004-11-02
申请号：US10786007
申请日：2004-02-26
申请人： Naoki Kobayashi , Shunichi Saeki , Hideaki Kurata
发明人： Naoki Kobayashi , Shunichi Saeki , Hideaki Kurata
IPC分类号： G11C1604
CPC分类号： G11C7/1078 , G11C7/1087 , G11C8/12 , G11C16/08 , G11C16/10 , G11C2216/14
摘要： A non-volatile memory device is provided which includes a flash memory having a plurality of banks and a bank selection register which can take on states at least equal in number to the number of banks. The bank selection register outputs a signal to point to one of the banks based upon one of the states of the bank selection register. A controller is also provided having a plurality of data buffers corresponding, respectively, to the banks. In addition to word lines, bit lines and memory cells, each bank includes a data register to temporarily hold data to be written to the memory cells. The controller transmits data in the data buffer to the data register of the pointed to bank, while the flash memory writes data held in the data register to the memory cells of another one of the banks.
摘要翻译：提供了一种非易失性存储器件，其包括具有多个存储体的闪速存储器和可选择与存储体数目至少相等的状态的存储体选择寄存器。存储体选择寄存器基于存储体选择寄存器的一种状态输出指向一组存储体的信号。还提供了具有分别对应于银行的多个数据缓冲器的控制器。除了字线，位线和存储单元之外，每个存储体都包括一个数据寄存器，用于临时保存要写入存储单元的数据。控制器将数据缓冲器中的数据发送到指向库的数据寄存器，而闪存将数据寄存器中保存的数据写入另一个存储体的存储单元。

10. 发明授权

US06714452B2 Non-volatile semiconductor memory device and semiconductor disk device 有权
标题翻译：非易失性半导体存储器件和半导体磁盘器件
公开(公告)号：US06714452B2
公开(公告)日：2004-03-30
申请号：US10205426
申请日：2002-07-26
申请人： Naoki Kobayashi , Shunichi Saeki , Hideaki Kurata
发明人： Naoki Kobayashi , Shunichi Saeki , Hideaki Kurata
IPC分类号： G11C1604
CPC分类号： G11C7/1078 , G11C7/1087 , G11C8/12 , G11C16/08 , G11C16/10 , G11C2216/14
摘要： A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.
摘要翻译：非易失性半导体存储器件能够使其单独的存储体与外部分开控制，并且半导体盘装置能够立即进行下一次写入已经准备就绪的非易失性半导体存储器件组。每个存储体具有从其数据寄存器到存储器单元的数据的独立写入操作，使得即使在其他存储体从数据寄存器写入其存储器的存储单元的写入操作期间也能够将数据从外部传送到存储体的数据寄存器。

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