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1. 发明申请

US20070195596A1 Semiconductor integrated circuit device, production and operation method thereof 有权
标题翻译：半导体集成电路器件，其生产和操作方法
公开(公告)号：US20070195596A1
公开(公告)日：2007-08-23
申请号：US11700085
申请日：2007-01-31
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0425 , G11C16/12 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.
摘要翻译：一种半导体集成器件，具有多个存储单元，每个存储单元包括通过绝缘膜形成在浮置栅极的侧表面上的浮置栅极，控制栅极和辅助栅极。耦合到选择的存储单元的辅助栅极用于产生热电子，并且与其他辅助栅极交替布置，其功能是防止未选择的存储器单元中的写入错误。

2. 发明授权

US06243290B1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06243290B1
公开(公告)日：2001-06-05
申请号：US09645878
申请日：2000-08-25
申请人： Hideaki Kurata , Naoki Kobayashi , Takashi Kobayashi , Katsutaka Kimura , Hitoshi Kume , Shunichi Saeki
发明人： Hideaki Kurata , Naoki Kobayashi , Takashi Kobayashi , Katsutaka Kimura , Hitoshi Kume , Shunichi Saeki
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C16/32 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5623 , G11C2211/5624 , G11C2211/5642
摘要： The present invention provides a nonvolatile semiconductor memory device for multilevel data storage that simultaneously carries out programming of multilevel data and subsequent verification at a high programming throughput. For this purpose, the present device includes a circuit 6 to hold programming data when programming is executed, a circuit 7 to generate timing signals to set up level-specific phases of verifying multilevel programming data during a verification period, a circuit 2 to increase stepwise the selected word line voltage during verification in accordance with the above timing signals, a circuit 4 to select target memory cells 1 for verification, depending on the data retrieved from the latch in accordance with the above timing signals, and verify whether the selected memory cells have been programmed on threshold voltage level, according to the energized or de-energized state thereof, and a circuit 5 to supply programming bias to the bit line to program data into insufficiently programmed memory cells, according to the verify results.
摘要翻译：本发明提供了一种用于多级数据存储的非易失性半导体存储器件，其以高编程吞吐量同时执行多级数据的编程和后续验证。为此，本设备包括：当执行编程时保存编程数据的电路6，电路7，用于产生定时信号，以在验证期间建立验证多电平编程数据的电平特定相位;电路2，根据上述定时信号在校验期间逐步增加所选择的字线电压;电路4，用于选择取决于根据上述定时信号从锁存器检索的数据，并且根据其通电或去激励状态来验证所选择的存储器单元是否已经被设置在阈值电压电平上，以及一个向位线提供编程偏置以将数据编程为不足的电路5 根据验证结果，编程好的内存单元。

3. 发明授权

US07366015B2 Semiconductor integrated circuit device, production and operation method thereof 有权
标题翻译：半导体集成电路器件，其生产和操作方法
公开(公告)号：US07366015B2
公开(公告)日：2008-04-29
申请号：US11700085
申请日：2007-01-31
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0425 , G11C16/12 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.
摘要翻译：一种半导体集成器件，具有多个存储单元，每个存储单元包括通过绝缘膜形成在浮置栅极的侧表面上的浮置栅极，控制栅极和辅助栅极。耦合到选择的存储单元的辅助栅极用于产生热电子，并且与其他辅助栅极交替布置，其功能是防止未选择的存储器单元中的写入错误。

4. 发明申请

US20050243603A1 Semiconductor integrated circuit device including first, second and third gates 有权
标题翻译：半导体集成电路器件包括第一，第二和第三栅极
公开(公告)号：US20050243603A1
公开(公告)日：2005-11-03
申请号：US11061843
申请日：2005-02-22
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C11/34 , G11C16/04 , G11C16/12 , H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0425 , G11C16/12 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.
摘要翻译：一种半导体集成器件，具有多个存储单元，每个存储单元包括通过绝缘膜形成在浮置栅极的侧表面上的浮置栅极，控制栅极和辅助栅极。耦合到选择的存储单元的辅助栅极用于产生热电子，并且与其他辅助栅极交替布置，其功能是防止未选择的存储器单元中的写入错误。

5. 发明授权

US06901006B1 Semiconductor integrated circuit device including first, second and third gates 失效
标题翻译：半导体集成电路器件包括第一，第二和第三栅极
公开(公告)号：US06901006B1
公开(公告)日：2005-05-31
申请号：US10674051
申请日：2003-09-30
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C11/34 , G11C16/04 , G11C16/12 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0425 , G11C16/12 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.
摘要翻译：在包括第三栅极的半导体集成电路器件中，本发明改进了小型化和操作速度并降低了绝缘膜的缺陷密度。在包括形成在半导体衬底中的第一导电类型阱的阱的半导体集成电路器件中，阱内部具有第二导电类型的源极/漏极扩散层，通过绝缘膜形成在半导体衬底上的浮置栅极，栅极通过绝缘体膜从浮栅形成并隔离，通过连接控制栅极和通过绝缘膜形成并与半导体衬底，浮栅和控制栅极隔离的第三栅极形成的字线并且不同于浮置栅极并且控制栅极，第三栅极被埋在垂直于字线和通道的方向上存在的浮动栅极的空间中。

6. 发明授权

US06687156B2 Semiconductor integrated circuit device, production and operation method thereof 有权
标题翻译：半导体集成电路器件，其生产和操作方法
公开(公告)号：US06687156B2
公开(公告)日：2004-02-03
申请号：US10206982
申请日：2002-07-30
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C700
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.
摘要翻译：在包括第三栅极的半导体集成电路器件中，本发明改进了小型化和操作速度并降低了绝缘膜的缺陷密度。在包括形成在半导体衬底中的第一导电类型阱的阱的半导体集成电路器件中，阱内部具有第二导电类型的源极/漏极扩散层，通过绝缘膜形成在半导体衬底上的浮置栅极，栅极通过绝缘体膜从浮栅形成并隔离，通过连接控制栅极和通过绝缘膜形成并与半导体衬底，浮栅和控制栅极隔离的第三栅极形成的字线并且不同于浮置栅极并且控制栅极，第三栅极被埋在垂直于字线和通道的方向上存在的浮动栅极的空间中。

7. 发明授权

US07180774B2 Semiconductor integrated circuit device including first, second and third gates 有权
标题翻译：半导体集成电路器件包括第一，第二和第三栅极
公开(公告)号：US07180774B2
公开(公告)日：2007-02-20
申请号：US11061843
申请日：2005-02-22
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0425 , G11C16/12 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.
摘要翻译：一种半导体集成器件，具有多个存储单元，每个存储单元包括通过绝缘膜形成在浮置栅极的侧表面上的浮置栅极，控制栅极和辅助栅极。耦合到选择的存储单元的辅助栅极用于产生热电子，并且与其他辅助栅极交替布置，其功能是防止未选择的存储器单元中的写入错误。

8. 发明授权

US06438028B1 Semiconductor integrated circuit device, production and operation method thereof 有权
标题翻译：半导体集成电路器件，其生产和操作方法
公开(公告)号：US06438028B1
公开(公告)日：2002-08-20
申请号：US09616072
申请日：2000-07-13
申请人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
发明人： Takashi Kobayashi , Hideaki Kurata , Naoki Kobayashi , Hitoshi Kume , Katsutaka Kimura , Shunichi Saeki
IPC分类号： G11C700
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115
摘要： In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.
摘要翻译：在包括第三栅极的半导体集成电路器件中，本发明改进了小型化和操作速度并降低了绝缘膜的缺陷密度。在包括形成在半导体衬底中的第一导电类型阱的阱的半导体集成电路器件中，阱内部具有第二导电类型的源极/漏极扩散层，通过绝缘膜形成在半导体衬底上的浮置栅极，栅极通过绝缘体膜从浮栅形成并隔离，通过连接控制栅极和通过绝缘膜形成并与半导体衬底，浮栅和控制栅极隔离的第三栅极形成的字线并且不同于浮置栅极并且控制栅极，第三栅极被埋在垂直于字线和通道的方向上存在的浮动栅极的空间中。

9. 发明授权

US06636437B2 Programming method of nonvolatile semiconductor memory device 有权
公开(公告)号：US06636437B2
公开(公告)日：2003-10-21
申请号：US10260407
申请日：2002-10-01
申请人： Naoki Kobayashi , Hideaki Kurata , Katsutaka Kimura , Takashi Kobayashi , Shunichi Saeki
发明人： Naoki Kobayashi , Hideaki Kurata , Katsutaka Kimura , Takashi Kobayashi , Shunichi Saeki
IPC分类号： G11C1604
CPC分类号： G11C11/5628
摘要： In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.

10. 发明授权

US06876577B2 Programming method of nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件的编程方法
公开(公告)号：US06876577B2
公开(公告)日：2005-04-05
申请号：US10644747
申请日：2003-08-21
申请人： Naoki Kobayashi , Hideaki Kurata , Katsutaka Kimura , Takashi Kobayashi , Shunichi Saeki
发明人： Naoki Kobayashi , Hideaki Kurata , Katsutaka Kimura , Takashi Kobayashi , Shunichi Saeki
IPC分类号： G11C16/02 , G11C11/56 , G11C16/00 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628
摘要： In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed starting from the data having the nearer threshold voltage to the erased state. When writing each of the data having the other threshold voltages, writing of the data is simultaneously performed to a memory cell to which the data having the remoter threshold voltage from the erased state (write #2 and write #3).
摘要翻译：在能够存储多值数据的非易失性半导体存储器件中，能够以高可靠性实现快速写入。在这样一种非易失性半导体存储器件中，通过设置数据的多个阈值电压将多值信息存储在一个存储单元中，在写入具有该数据的数据之前，将具有最远的阈值电压的数据写入擦除状态其他阈值电压（写＃1）。然后从具有更接近的阈值电压的数据开始到擦除状态，顺序地执行具有其它阈值电压的数据的写入。当写入具有其他阈值电压的每个数据时，数据的写入同时执行到具有来自擦除状态的远程阈值电压的数据（写＃2和写＃3）的存储单元。

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