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1. 发明授权

US06797566B1 Semiconductor integrated circuit device and process for producing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06797566B1
公开(公告)日：2004-09-28
申请号：US10031117
申请日：2002-01-16
申请人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
发明人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7881
摘要： A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed in first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.
摘要翻译：具有第三栅极的半导体集成电路器件包括形成在第一导电型阱201中的第二导电型源极/漏极扩散层区域205，通过绝缘膜202形成在半导体衬底200上的浮动栅极203b，形成在浮动栅极203b上的控制栅极211b 通过半导体衬底，浮置栅极，控制栅极和绝缘膜形成的与浮置栅极和控制栅极不同的氮引入氧化硅膜210a和第三栅极207a，其中第三栅极形成为填充在第存在于字线和通道的垂直方向上的浮动栅极以及如此形成的第三栅极207a的高度低于浮置栅极203b的高度，改善了编程/擦除周期后存储单元尺寸和操作速度的降低以及改进的可靠性。

2. 发明申请

US20060275986A1 Semiconductor intergrated circuit device and process for producing the same 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20060275986A1
公开(公告)日：2006-12-07
申请号：US11499756
申请日：2006-08-07
申请人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
发明人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7881
摘要： A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.
摘要翻译：具有第三栅极的半导体集成电路器件包括形成在第一导电型阱201的第二导电型源极/漏极扩散层区域205，通过绝缘膜202形成在半导体衬底200上的浮置栅极203b，形成在浮动栅极203上的控制栅极211a b通过氮引入氧化硅膜210a和与通过半导体衬底，浮栅，控制栅极和绝缘膜形成的浮栅和控制栅极不同的第三栅极207a，其中第三栅极形成为填充在垂直方向上存在的浮动栅极与字线和沟道之间的间隙以及如此形成的第三栅极207a的高度低于浮动栅极203b的高度，具有改善的存储单元尺寸和操作速度的降低和改进编程/擦除周期后的可靠性。

3. 发明授权

US5694358A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5694358A
公开(公告)日：1997-12-02
申请号：US706267
申请日：1996-09-24
申请人： Takayuki Kawahara , Yusuke Jyouno , Syunichi Saeki , Naoki Miyamoto , Katsutaka Kimura
发明人： Takayuki Kawahara , Yusuke Jyouno , Syunichi Saeki , Naoki Miyamoto , Katsutaka Kimura
IPC分类号： G11C17/00 , G11C7/18 , G11C16/06 , G11C16/26 , G11C7/00
CPC分类号： G11C16/26 , G11C7/18
摘要： This invention provides a nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing the word line, and a plurality of memory cells including MOS transistors. Each of control gates of the MOS transistors are coupled to the word line and each of drains thereof are coupled to the bit lines, respectively. Each of the MOS transistors also has a floating gate. Further, the non-volatile semiconductor memory device comprises latch circuits, first switches, a sense amplifier coupled to the plurality of bit lines in common, and second switches. The latch circuits are coupled to the plurality of bit lines through the first switches which are coupled between the plurality of bit lines and the latch circuits, respectively. The second switches are respectively coupled between the plurality of bit lines and the sense amplifier, thereby coupling the sense amplifier to the bit lines. Each of the plurality of first switches includes a MOS transistor whose source-drain path is between a corresponding one of the plurality of bit lines and a corresponding one of the latch circuits, respectively. When data is to be read from a memory cell selected out of the plurality of memory cells, the plurality of first switches are turned off and one of the second switches between the selected memory cell and the sense amplifier is turned on.
摘要翻译：本发明提供一种具有字线，与字线交叉的多个位线以及包括MOS晶体管的多个存储单元的非易失性半导体存储器件。 MOS晶体管的每个控制栅极耦合到字线，并且其每个漏极分别耦合到位线。每个MOS晶体管也具有浮动栅极。此外，非易失性半导体存储器件包括锁存电路，第一开关，共同耦合到多个位线的读出放大器和第二开关。锁存电路通过分别耦合在多个位线和锁存电路之间的第一开关耦合到多个位线。第二开关分别耦合在多个位线和读出放大器之间，从而将读出放大器耦合到位线。多个第一开关中的每一个包括MOS晶体管，其源极 - 漏极路径分别位于多个位线中的相应一个位线和相应的一个锁存电路之间。当要从多个存储单元中选择的存储单元读取数据时，多个第一开关被截止，并且所选存储单元和读出放大器之间的第二开关中的一个导通。

4. 发明授权

US07105409B2 Semiconductor integrated circuit device and process for producing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07105409B2
公开(公告)日：2006-09-12
申请号：US10899119
申请日：2004-07-27
申请人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
发明人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7881
摘要： A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.
摘要翻译：具有第三栅极的半导体集成电路器件包括形成在第一导电型阱201的第二导电型源极/漏极扩散层区域205，通过绝缘膜202形成在半导体衬底200上的浮置栅极203b，形成在浮动栅极203上的控制栅极211a b通过氮导入氧化硅膜210a和与通过半导体衬底，浮栅，控制栅极和绝缘膜形成的浮栅和控制栅极不同的第三栅极207a，其中第三栅极形成为填充在垂直方向上存在的浮动栅极与字线和沟道之间的间隙以及如此形成的第三栅极207a的高度低于浮动栅极203b的高度，具有改善的存储单元尺寸和操作速度的降低和改进编程/擦除周期后的可靠性。

5. 发明申请

US20050014326A1 Semiconductor integrated circuit device and process for producing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20050014326A1
公开(公告)日：2005-01-20
申请号：US10899119
申请日：2004-07-27
申请人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
发明人： Takashi Kobayashi , Yasushi Goto , Tokuo Kure , Hideaki Kurata , Hitoshi Kume , Katsutaka Kimura , Syunichi Saeki
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7881
摘要： A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.
摘要翻译：具有第三栅极的半导体集成电路器件包括形成在第一导电型阱201的第二导电型源极/漏极扩散层区域205，通过绝缘膜202形成在半导体衬底200上的浮动栅极203b，通过氮气形成在浮动栅极203b上的控制栅极211a 引入与通过半导体衬底，浮动栅极，控制栅极和绝缘膜形成的浮动栅极和控制栅极不同的氧化硅膜210a和第三栅极207a，其中第三栅极形成为填充在第存在于字线和沟道的垂直方向的浮动栅极和由此形成的第三栅极207a的高度低于浮置栅极203b的高度，改善了编程/擦除周期后存储单元尺寸和操作速度的降低以及改进的可靠性。

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