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    • 2. 发明授权
    • Digital signal clock recovery
    • 数字信号时钟恢复
    • US5943378A
    • 1999-08-24
    • US691081
    • 1996-08-01
    • James Michael KebaClinton C. Powell, II
    • James Michael KebaClinton C. Powell, II
    • H04L7/00H04L7/033
    • H04L7/0334H04L7/0083
    • A clock recovery circuit for recovering a symbol clock (226) includes a level decoder (210) for determining one of a plurality of received states of a demodulated signal (105) during each symbol period of the symbol clock (226). Each of the plurality of received states corresponds to one of at least two modulation levels. The level decoder (210) generates for each of the plurality of received states a sign signal (212) having transitions at central threshold transition times and a magnitude signal (211). An edge selector (220) determines selected central threshold transition times. A synchronizable clock (225) is synchronized by the selected central threshold transition times, resulting in a significant reduction of symbol clock (226) jitter.
    • 用于恢复符号时钟(226)的时钟恢复电路包括用于在符号时钟(226)的每个符号周期期间确定解调信号(105)的多个接收状态之一的电平解码器(210)。 多个接收状态中的每一个对应于至少两个调制电平之一。 电平解码器(210)针对多个接收状态中的每一个生成在中心阈值转换时间具有转变的符号信号(212)和幅度信号(211)。 边缘选择器(220)确定所选择的中心阈值转换时间。 同步时钟(225)通过所选择的中央阈值转换时间同步,导致符号时钟(226)抖动的显着减少。
    • 9. 发明授权
    • Method and apparatus for decoding a two-level radio signal
    • 用于解码两电平无线电信号的方法和装置
    • US5799043A
    • 1998-08-25
    • US867498
    • 1997-06-02
    • Chun-Ye Susan ChangJames Rodney WebsterClinton C. Powell, II
    • Chun-Ye Susan ChangJames Rodney WebsterClinton C. Powell, II
    • H04L25/06H04L25/48H04L25/34
    • H04L25/062
    • A selective call unit (800) comprising a receiver (100) and a processor (810) is used for decoding a 2-level radio signal. The processor (810) is adapted to convert in-phase and quadrature signals generated by the receiver (100) to a sequence of state transitions representative of the plurality of symbols. For each symbol in the plurality of symbols, the processor (810) counts the sequence of state transitions during a symbol period, and compares the recorded count to a predetermined threshold, thereby generating a comparison result. The processor (810) then calculates a bit decision threshold level based on an average of the comparison result for each symbol in the plurality of symbols. For each symbol in a plurality of subsequent symbols, the processor (810) then compares the bit decision threshold level to the sequence of state transitions counted during a symbol period to decode a digital logic level therefrom.
    • 包括接收机(100)和处理器(810)的选呼单元(800)用于对2级无线电信号进行解码。 处理器(810)适于将由接收机(100)产生的同相和正交信号转换为表示多个符号的状态转换序列。 对于多个符号中的每个符号,处理器(810)在符号周期期间对状态转换序列进行计数,并将记录的计数与预定阈值进行比较,从而生成比较结果。 然后,处理器(810)基于多个符号中的每个符号的比较结果的平均值来计算比特判定阈值水平。 对于多个后续符号中的每个符号,处理器(810)然后将比特判定阈值电平与在符号周期期间计数的状态转换序列进行比较,以从其中解码数字逻辑电平。