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1. 发明授权

US06654594B1 Digitized automatic gain control system and methods for a controlled gain receiver 失效
标题翻译：数字化自动增益控制系统和受控增益接收器的方法
公开(公告)号：US06654594B1
公开(公告)日：2003-11-25
申请号：US09580770
申请日：2000-05-30
申请人： James David Hughes , John Richard Oakley , Clinton C Powell, II
发明人： James David Hughes , John Richard Oakley , Clinton C Powell, II
IPC分类号： H04B106
CPC分类号： H03G3/3089 , H03G3/001 , H04B17/318 , H04W52/52
摘要： An automatic gain control (AGC) system (100) for a controlled gain receiver (1101) includes a magnitude generator (160) and a gain corrector (170). The magnitude generator (160) generates a binary voltage squared signal (165) having a binary value that is directly proportional to a recovered signal power of an intercepted signal (113). The gain corrector (170) determines an adjustment of a gain control value (195) as a multiple of increments that are approximately 3 decibel (dB), by shifting (475, 445) a reference threshold by one or more bits and comparing (485, 455) the shifted reference threshold to the binary voltage squared signal. An initial setting of a state of a step attenuator (114) during a track mode (172) is determined during a warm up mode (171) by comparing the binary voltage squared signal (165) to two different thresholds (245, 255).
摘要翻译：用于受控增益接收器（1101）的自动增益控制（AGC）系统（100）包括幅度发生器（160）和增益校正器（170）。幅度发生器（160）产生二进制电压平方信号（165），二进制值与被截获信号（113）的恢复信号功率成正比。增益校正器（170）通过将参考阈值移位（475,445）一个或多个比特并且比较（485（445）），将增益控制值（195）的调整确定为大约3分贝（dB）的增量的倍数，455）移位的参考阈值到二进制电压平方信号。通过将二进制电压平方信号（165）与两个不同阈值（245,255）进行比较，在预热模式（171）期间，确定在轨道模式（172）期间阶梯衰减器（114）的状态的初始设置。

2. 发明授权

US6130920A Method and apparatus for accurate synchronization using symbol decision feedback 失效
标题翻译：使用符号决策反馈进行精确同步的方法和装置
公开(公告)号：US6130920A
公开(公告)日：2000-10-10
申请号：US76992
申请日：1998-05-13
申请人： Clinton C. Powell, II , Chun-Ye Chang , David L. Brown , David F. Brown , Robert Karl Schweickert
发明人： Clinton C. Powell, II , Chun-Ye Chang , David L. Brown , David F. Brown , Robert Karl Schweickert
IPC分类号： H03M13/39 , H03M13/23 , H04L7/00 , H04L7/02 , H04L7/04 , H04L25/38 , H04L27/06 , H04L27/14
CPC分类号： H04L7/0062 , H04L7/042
摘要： A circuit (12) for symbol decision directed feedback synchronization includes a current synchonization clock (45) that provides an initial sampling point and selects a detector corresponding to a current symbol decision. The circuit further includes a plurality of detectors (31, 32, 33, and 34) including the detector corresponding to the current symbol decision, a buffer (736) for storing the output of the detector corresponding to the current symbol decision and a processor (300) for seeking within a predetermined window about the initial sampling point for an optimum phase value to provide an adjustment signal which is used by the processor to adjust a subsequent symbol's sychronization clock to provide an optimal sampling point.
摘要翻译：用于符号决定定向反馈同步的电路（12）包括提供初始采样点并选择对应于当前符号判定的检测器的当前同步时钟（45）。电路还包括多个包括与当前符号决定相对应的检测器的检测器（31,32,33和34），用于存储与当前符号判定相对应的检测器的输出的缓冲器（736） 300），用于在关于初始采样点的预定窗口内寻找最佳相位值，以提供由处理器用于调整后续符号的同步时钟以提供最佳采样点的调整信号。

3. 发明授权

US6084931A Symbol synchronizer based on eye pattern characteristics having variable adaptation rate and adjustable jitter control, and method therefor 失效
标题翻译：基于具有可变自适应速率和可调节抖动控制的眼图特征的符号同步器及其方法
公开(公告)号：US6084931A
公开(公告)日：2000-07-04
申请号：US962267
申请日：1997-10-31
申请人： Clinton C. Powell, II , James M. Keba , James R. Webster
发明人： Clinton C. Powell, II , James M. Keba , James R. Webster
IPC分类号： H04L7/033 , H04L7/00
CPC分类号： H04L7/0334 , H04L7/007
摘要： A symbol synchronizer (10) for use in a communication device. The symbol synchronizer (10) comprises a sampling circuit (100) which samples the demodulated signal at a plurality of sampling events for each symbol period to generate three sample values at each sampling event. An eye pattern detector circuit (200) generates eye pattern characteristic information based on the three sample values, and outputs a symbol pulse in response to detecting eye pattern characteristic information consistent with a symbol center. A synchronization noise mask circuit (400) filters symbol pulses that occur during a predetermined period of time after a first symbol pulse is detected for each symbol period. A synchronization adjust circuit (500) generates a synchronization pulse during each symbol period at a particular instant of time during the symbol period based on a history of the occurrences of symbol pulses for a current symbol period and for prior symbol periods.
摘要翻译：一种用于通信设备的符号同步器（10）。符号同步器（10）包括采样电路（100），其对于每个符号周期的多个采样事件对解调信号进行采样，以在每个采样事件处产生三个采样值。眼图检测器电路（200）基于三个采样值产生眼图特征信息，并且响应于与符号中心一致的检测眼图特征信息而输出符号脉冲。同步噪声屏蔽电路（400）对每个符号周期检测到第一个符号脉冲之后的预定时间段内的符号脉冲进行滤波。同步调整电路（500）在符号周期内的特定时刻的每个符号周期期间，基于当前符号周期的符号脉冲的历史和先前的符号周期来生成同步脉冲。

4. 发明授权

US5710975A Selective call transceiver with system approved power saving state 失效
标题翻译：具有系统认可省电状态的选择性呼叫收发器
公开(公告)号：US5710975A
公开(公告)日：1998-01-20
申请号：US578755
申请日：1995-12-26
申请人： Richard C. Bernhardt , Clinton C. Powell, II
发明人： Richard C. Bernhardt , Clinton C. Powell, II
IPC分类号： H04W84/02 , H04W88/02 , H04Q7/14
CPC分类号： H04W84/025 , H04W88/022 , Y02B60/50
摘要： A battery-powered selective call transceiver, operating in two-way communication with an RF communication system, can be put in a power saving state. A user control on the transceiver allows a user to select the duration of a power saving interval. The transceiver sends to the communication system a signal requesting that the transceiver enter a power saving state for the selected interval. Upon receipt of an acknowledgment signal from the system, the transceiver enters the power saving state.
摘要翻译：可以将与RF通信系统进行双向通信操作的电池供电的选择性呼叫收发器置于省电状态。收发器上的用户控制允许用户选择节电间隔的持续时间。收发器向通信系统发送请求收发器在所选间隔内进入省电状态的信号。收到来自系统的确认信号后，收发器进入省电状态。

5. 发明授权

US5673197A Apparatus and method for updating thresholds for peak and valley systems 失效
标题翻译：用于更新峰谷系统阈值的装置和方法
公开(公告)号：US5673197A
公开(公告)日：1997-09-30
申请号：US495857
申请日：1995-06-28
申请人： James Michael Keba , Clinton C. Powell, II
发明人： James Michael Keba , Clinton C. Powell, II
IPC分类号： H04L25/06 , G06F19/00
CPC分类号： H04L25/062
摘要： An apparatus and method for updating upper and lower thresholds in peak and valley systems. The apparatus includes comparators which determine which peaks or valleys are eligible for use in the calculation of upper or lower threshold levels. The comparators output the eligible peaks and valleys into statistical blocks that calculate the mean of the peaks and valleys as well as the deviation over a predetermined number of samples. Additional comparators compare either the mean deviation, standard deviation, or variance of the eligible peaks and valleys to predetermined deviation thresholds to determine whether the mean peak or mean valley should be used to calculate update thresholds. The apparatus further includes memory elements that store the mean peak or mean valley values used in the calculation of upper or lower thresholds.
摘要翻译：一种用于更新峰谷系统中上限和下限阈值的装置和方法。该装置包括比较器，其确定哪些峰或谷有资格用于计算上限或下限阈值水平。比较器将合格的峰和谷输出到计算峰和谷的平均值以及预定数量样本的偏差的统计块中。额外的比较器可将平均偏差，标准偏差或符合条件的峰谷的方差与预定的偏差阈值进行比较，以确定平均峰值还是平均谷值应用于计算更新阈值。该装置还包括存储元件，其存储在计算上限或下限阈值时使用的平均峰值或平均谷值。

6. 发明授权

US5309480A Non-coherent quadrature demodulation of MSK signals 失效
标题翻译： MSK信号的非相干正交解调
公开(公告)号：US5309480A
公开(公告)日：1994-05-03
申请号：US70486
申请日：1993-06-02
申请人： Clinton C. Powell, II , Joseph Boccuzzi
发明人： Clinton C. Powell, II , Joseph Boccuzzi
IPC分类号： H04L27/233 , H04L27/14
CPC分类号： H04L27/2332
摘要： Briefly, according to the invention, a receiver (100) for receiving a carrier signal MSK (minimum shift keying) modulated with a bit stream of a digital information signal (302) is disclosed. The receiver (100) comprises a quadrature demodulator (128) for providing baseband quadrature demodulated signals (306 and 308). The quadrature demodulated (128) is coupled to an EXOR (126) for providing a decoded bit stream of the digital information signal (312) thereby avoiding complex decoder circuits. The quadrature demodulator (128) includes a pair of mixers (106 and 108) for quadrature mixing the received carrier signal and a pair of filters (114 and 118) for filtering the outputs of the mixers (106 and 108). The filters (114 and 118) are coupled to a pair of limiters (116 and 120) for limiting the filtered signals.
摘要翻译：简而言之，根据本发明，公开了一种用于接收用数字信息信号（302）的比特流调制的载波信号MSK（最小移位键控）的接收机（100）。接收器（100）包括用于提供基带正交解调信号（306和308）的正交解调器（128）。正交解调（128）耦合到EXOR（126），用于提供数字信息信号（312）的解码比特流，从而避免复杂的解码器电路。正交解调器（128）包括用于正交混合接收的载波信号的一对混频器（106和108）和用于对混频器（106和108）的输出进行滤波的一对滤波器（114和118）。滤波器（114和118）耦合到一对限制器（116和120），用于限制经滤波的信号。

7. 发明授权

US06996383B2 Digitized automatic gain control system and methods for a controlled gain receiver 有权
标题翻译：数字化自动增益控制系统和受控增益接收器的方法
公开(公告)号：US06996383B2
公开(公告)日：2006-02-07
申请号：US10346611
申请日：2003-01-17
申请人： James David Hughes , John Richard Oakley , Clinton C Powell, II
发明人： James David Hughes , John Richard Oakley , Clinton C Powell, II
IPC分类号： H04B17/02
CPC分类号： H03G3/3089 , H03G3/001 , H04B17/318 , H04W52/52
摘要： An automatic gain control (AGC) system (100) for a controlled gain receiver (1101) includes a magnitude generator (160) and a gain corrector (170). The magnitude generator (160) generates a binary voltage squared signal (165) having a binary value that is directly proportional to a recovered signal power of an intercepted signal (113). The gain corrector (170) determines an adjustment of a gain control value (195) as a multiple of increments that are approximately 3 decibel (dB), by shifting (475, 445) a reference threshold by one or more bits and comparing (485, 455) the shifted reference threshold to the binary voltage squared signal. An initial setting of a state of a step attenuator (114) during a track mode (172) is determined during a warm up mode (171) by comparing the binary voltage squared signal (165) to two different thresholds (245, 255). A filter (162) accommodates a variety of bandwidths and symbol rates by settings of an accumulator (505) and scaler (510) that are included in the filter (162). A received signal strength indicator function (182) of the controlled gain receiver (1101) generates a low resolution or high resolution RSSI signal (183), depending on the mode. The value of the low resolution RSSI signal (183) is directly proportional to the power of the intercepted signal (113).
摘要翻译：用于受控增益接收器（1101）的自动增益控制（AGC）系统（100）包括幅度发生器（160）和增益校正器（170）。幅度发生器（160）产生二进制电压平方信号（165），二进制值与被截获信号（113）的恢复信号功率成正比。增益校正器（170）通过将参考阈值移位（475,445）一个或多个比特并且比较（485（445）），将增益控制值（195）的调整确定为大约3分贝（dB）的增量的倍数，455）移位的参考阈值到二进制电压平方信号。通过将二进制电压平方信号（165）与两个不同阈值（245,255）进行比较，在预热模式（171）期间，确定在轨道模式（172）期间阶梯衰减器（114）的状态的初始设置。滤波器（162）通过包括在滤波器（162）中的累加器（505）和缩放器（510）的设置来适应各种带宽和符号率。根据该模式，受控增益接收器（1101）的接收信号强度指示功能（182）产生低分辨率或高分辨率RSSI信号（183）。低分辨率RSSI信号（183）的值与截取的信号（113）的功率成正比。

8. 发明授权

US06570938B1 Method and apparatus for recovering data symbols from a signal received by a radio communication device 失效
标题翻译：用于从由无线电通信装置接收的信号中恢复数据符号的方法和装置
公开(公告)号：US06570938B1
公开(公告)日：2003-05-27
申请号：US08641396
申请日：1996-05-01
申请人： Joseph Boccuzzi , Clinton C Powell, II
发明人： Joseph Boccuzzi , Clinton C Powell, II
IPC分类号： H03D100
CPC分类号： H04L27/1525
摘要： A signal processor (125) for recovering data symbols from a received signal includes matched filters (210, 215) for receiving and filtering a quadrature (Q) signal component of the received signal. A detector (225) is coupled to the matched filters (210, 215) for selecting a filtered signal provided by one of the matched filters (210, 215) and for labeling the filtered signal according to a magnitude and phase of the filtered signal to provide a Q channel output flag. A Q channel symbol/sign decoder (235) then processes the Q channel output flag to generate a Q channel magnitude variable and a polarity variable, and a symbol decoder (240) coupled to the Q channel symbol/sign decoder (235) generates a data symbol in accordance with the Q channel magnitude variable and the polarity variable.
摘要翻译：用于从接收信号中恢复数据符号的信号处理器（125）包括用于接收和滤波接收信号的正交（Q）信号分量的匹配滤波器（210,215）。检测器（225）耦合到匹配滤波器（210,215），用于选择由匹配滤波器（210,215）之一提供的滤波信号，并根据滤波信号的幅度和相位对滤波信号进行标号提供Q通道输出标志。 AQ信道符号/符号解码器（235）然后处理Q信道输出标志以产生Q信道幅度变量和极性变量，耦合到Q信道符号/符号解码器（235）的符号解码器（240）产生数据符号根据Q通道幅度变量和极性变量。

9. 发明授权

US6111855A Method and apparatus for baud detection in a communication device 失效
标题翻译：通信设备中波特率检测的方法和装置
公开(公告)号：US6111855A
公开(公告)日：2000-08-29
申请号：US128161
申请日：1998-08-03
申请人： Chun-Ye Susan Chang , Clinton C Powell, II
发明人： Chun-Ye Susan Chang , Clinton C Powell, II
IPC分类号： H04L25/02 , H04J3/14
CPC分类号： H04L25/0262
摘要： A method (500) of baud detection in a communication device (700) includes the steps of sorting phase pulses among overlapping sets of time slots (502) and counting phase pulses within each of the overlapping sets of time slots creating corresponding counter values (504). Then, counter values are compared with predetermined thresholds (506-512), wherein a baud pass condition (570) is met when at least one counter has a counter value exceeding an upper threshold and wherein a counter N/2 positions away has a counter value below a lower threshold. The baud pass condition may he further conditioned on meeting the requirement that at least another counter value falls below a middle threshold.
摘要翻译：在通信设备（700）中的波特率检测的方法（500）包括以下步骤：对重叠的时隙集合（502）中的相位脉冲进行排序，并计算每个重叠的时隙集合内的相位脉冲，产生相应的计数器值（504 ）。然后，将计数器值与预定阈值（506-512）进行比较，其中当至少一个计数器具有超过上阈值的计数器值时，满足波特率条件（570），并且其中远离计数器N / 2的位置具有计数器值低于较低的阈值。波特率通过条件可能进一步受限于满足至少另一个计数器值低于中间阈值的要求。

10. 发明授权

US5943378A Digital signal clock recovery 失效
标题翻译：数字信号时钟恢复
公开(公告)号：US5943378A
公开(公告)日：1999-08-24
申请号：US691081
申请日：1996-08-01
申请人： James Michael Keba , Clinton C. Powell, II
发明人： James Michael Keba , Clinton C. Powell, II
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/0334 , H04L7/0083
摘要： A clock recovery circuit for recovering a symbol clock (226) includes a level decoder (210) for determining one of a plurality of received states of a demodulated signal (105) during each symbol period of the symbol clock (226). Each of the plurality of received states corresponds to one of at least two modulation levels. The level decoder (210) generates for each of the plurality of received states a sign signal (212) having transitions at central threshold transition times and a magnitude signal (211). An edge selector (220) determines selected central threshold transition times. A synchronizable clock (225) is synchronized by the selected central threshold transition times, resulting in a significant reduction of symbol clock (226) jitter.
摘要翻译：用于恢复符号时钟（226）的时钟恢复电路包括用于在符号时钟（226）的每个符号周期期间确定解调信号（105）的多个接收状态之一的电平解码器（210）。多个接收状态中的每一个对应于至少两个调制电平之一。电平解码器（210）针对多个接收状态中的每一个生成在中心阈值转换时间具有转变的符号信号（212）和幅度信号（211）。边缘选择器（220）确定所选择的中心阈值转换时间。同步时钟（225）通过所选择的中央阈值转换时间同步，导致符号时钟（226）抖动的显着减少。

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