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1. 发明授权

US06809676B1 Method and system for VCO-based analog-to-digital conversion (ADC) 有权
标题翻译：基于VCO的模数转换（ADC）的方法和系统
公开(公告)号：US06809676B1
公开(公告)日：2004-10-26
申请号：US10224977
申请日：2002-08-20
申请人： Ahmed Younis , Marwan M. Hassoun , Moises E. Robinson
发明人： Ahmed Younis , Marwan M. Hassoun , Moises E. Robinson
IPC分类号： H03M160
CPC分类号： H03M1/60
摘要： A VCO (110) can be configured to convert an analog input signal (105) to a digital output signal (125). In accordance with the inventive arrangements, the VCO can convert the analog input signal to at least one intermediate signal (130) having a frequency dependent on the analog input signal. A frequency detector (115) can be configured to determine a frequency of at least one intermediate signal. Subsequently, a mapping circuit (120) can be configured to map the determined frequency of the at least one intermediate signal to an output value representing the digital output signal (125).
摘要翻译： VCO（110）可以被配置为将模拟输入信号（105）转换成数字输出信号（125）。根据本发明的结构，VCO可以将模拟输入信号转换成具有取决于模拟输入信号的频率的至少一个中间信号（130）。频率检测器（115）可被配置为确定至少一个中间信号的频率。随后，映射电路（120）可以被配置为将所确定的至少一个中间信号的频率映射到表示数字输出信号（125）的输出值。

2. 发明授权

US06501339B1 Ring oscillators with improved signal-path matching for high-speed data communications 有权
标题翻译：环形振荡器具有改进的信号路径匹配，用于高速数据通信
公开(公告)号：US06501339B1
公开(公告)日：2002-12-31
申请号：US09927146
申请日：2001-08-10
申请人： Ahmed Younis , Moises E. Robinson , Michael A. Nix , Brian T. Brunn
发明人： Ahmed Younis , Moises E. Robinson , Michael A. Nix , Brian T. Brunn
IPC分类号： H03B524
CPC分类号： H03L7/0995 , H03K3/0315 , H03L7/087 , H03L7/0891 , H03L7/18
摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data from one device to another. Many such devices include a ring oscillator, a circuit that generates one or more oscillating signals using a series of interconnected delay circuits. One problem with conventional ring oscillators concerns differences in the signal paths between the delay circuits. Accordingly, the present inventors devised several oscillators having unique layouts, which reduce differences in the signal paths between delay circuits. One exemplary oscillator includes a sequence of delay circuits having input-output connections between at least two pairs of non-adjacent delay circuits. Another exemplary oscillator provides two groups of delay circuits with a bus between the two groups, intercoupling the circuits. And, another exemplary oscillator arranges three or more delay circuits to form a closed loop. Applications for these oscillators include not only receivers, transmitters, and transceivers, but also programmable integrated circuits, electronic devices, and systems.
摘要翻译：电子设备通常耦合在一起以作为需要从一个设备到另一个设备的数据通信的系统进行操作。许多这样的设备包括环形振荡器，使用一系列互连的延迟电路产生一个或多个振荡信号的电路。常规环形振荡器的一个问题涉及延迟电路之间的信号路径的差异。因此，本发明人设计了具有独特布局的几个振荡器，其减小延迟电路之间的信号路径的差异。一个示例性振荡器包括在至少两对非相邻延迟电路之间具有输入 - 输出连接的延迟电路序列。另一个示例性振荡器提供两组延迟电路，其中两组之间的总线相互耦合。并且，另一示例性振荡器布置三个或更多个延迟电路以形成闭环。这些振荡器的应用不仅包括接收器，发射器和收发器，还包括可编程集成电路，电子设备和系统。

3. 发明授权

US06504415B1 Clock distribution for improved jitter performance in high-speed communication circuits 有权
标题翻译：时钟分配，用于改善高速通信电路中的抖动性能
公开(公告)号：US06504415B1
公开(公告)日：2003-01-07
申请号：US09941968
申请日：2001-08-28
申请人： Moises E. Robinson , Ahmed Younis
发明人： Moises E. Robinson , Ahmed Younis
IPC分类号： G06F104
CPC分类号： G06F1/10 , G06F5/06
摘要： In many electronic systems, it is common to communicate data from a transmitter in one device to a receiver in another. Accurate communications requires use of several matched clock signals. Mismatches in these clock signals cause transmitters to add “jitter” to transmitted data or receivers to be more intolerant of jitter in received signals, increasing the chances of mis-interpreting the data. Accordingly, the inventors devised an exemplary clock-distribution method which entails generating a base set of matched clock signals, deriving at least two separate sets of matched clock signals from the base set, and distributing one of the sets of clock signals to a set of matched components in a circuit and the other set of matched clock signals to a different set of components in the same circuit. The clock signals driving the matched components are isolated from mismatched aspects of the other components, and thus exhibit better matching. This method improves the accuracy of high-speed receivers, transmitters, transceivers, and other communications circuits that use it.
摘要翻译：在许多电子系统中，通常将数据从一个设备中的发射机传送到另一个设备中的接收机。精确的通信需要使用几个匹配的时钟信号。这些时钟信号中的不匹配会导致发射机将“抖动”添加到传输的数据或接收器，以便更加不容忍接收信号中的抖动，从而增加了错误解释数据的可能性。因此，发明人设计了一种示例性的时钟分配方法，该方法需要产生一组匹配的时钟信号，从基本集合导出至少两组分离的匹配的时钟信号，并将这些时钟信号组中的一组分配给电路中的匹配组件和另一组匹配的时钟信号到同一电路中的一组不同组件。驱动匹配组件的时钟信号与其他组件的不匹配的方面是隔离的，因此表现出更好的匹配。该方法提高了高速接收机，发射机，收发器和其他使用它的通信电路的精度。

4. 发明授权

US07058120B1 Integrated high-speed serial-to-parallel and parallel-to-serial transceiver 有权
标题翻译：集成的高速串并行和并行到串行收发器
公开(公告)号：US07058120B1
公开(公告)日：2006-06-06
申请号：US10051222
申请日：2002-01-18
申请人： Jinghui Lu , Shahriar Rokhsaz , Stephen D. Anderson , Michael A. Nix , Ahmed Younis , Michael Ren Kent , Yvette P. Lee , Firas N. Abughazaleh , Brian T. Brunn , Moises E. Robinson , Kazi S. Hossain
发明人： Jinghui Lu , Shahriar Rokhsaz , Stephen D. Anderson , Michael A. Nix , Ahmed Younis , Michael Ren Kent , Yvette P. Lee , Firas N. Abughazaleh , Brian T. Brunn , Moises E. Robinson , Kazi S. Hossain
IPC分类号： H03K11/00 , H04L25/60 , H04L25/64
CPC分类号： H03L7/093 , H03K5/1565 , H03M9/00 , H04L7/0004 , H04L7/033 , H04W4/18
摘要： A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.
摘要翻译：收发机包括接收机部分和发射机部分。接收器部分包括时钟电路，串行到并行模块和补偿。发射机部分包括时钟电路，并行到串行模块和补偿。接收器部分和发射器部分内的补偿补偿了时钟控制电路，串行到并行模块和并行到串行模块的集成电路（IC）处理限制和/或集成电路（IC）制造限制，否则限制收发器可以传输数据的速度。

5. 发明授权

US07224760B1 High-speed wide bandwidth data detection circuit 有权
标题翻译：高速宽带数据检测电路
公开(公告)号：US07224760B1
公开(公告)日：2007-05-29
申请号：US10421512
申请日：2003-04-22
申请人： Shahriar Rokhsaz , Moises E. Robinson , Ahmed Younis , Brian T. Brunn
发明人： Shahriar Rokhsaz , Moises E. Robinson , Ahmed Younis , Brian T. Brunn
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H03D13/003 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/10
摘要： A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.
摘要翻译：高速，宽带宽数据检测电路包括相位检测模块，数据检测模块，环路滤波器和压控振荡器。相位检测模块可操作地耦合以基于对输入数据流和恢复的时钟之间的差异的当前模式数学操作产生受控电流。相位检测模块执行当前模式的数学操作并产生当前域中的受控电流。数据检测模块可操作地耦合以基于输入数据流和恢复的时钟产生检测到的数据。环路滤波器可操作地耦合以将受控电流转换成受控电压。压控振荡器可操作地耦合以将控制电压转换成恢复的时钟。

6. 发明授权

US07092480B1 High-speed synchronous counters with reduced logic complexity 有权
公开(公告)号：US07092480B1
公开(公告)日：2006-08-15
申请号：US10977304
申请日：2004-10-29
申请人： Ahmed Younis
发明人： Ahmed Younis
IPC分类号： H03K23/54 , H03H11/26
CPC分类号： H03K23/54 , H03K23/548 , H03K23/588
摘要： Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

7. 发明授权

US06956923B1 High speed phase detector architecture 有权
标题翻译：高速相位检测器架构
公开(公告)号：US06956923B1
公开(公告)日：2005-10-18
申请号：US10421247
申请日：2003-04-22
申请人： Ahmed Younis , Shahriar Rokhsaz
发明人： Ahmed Younis , Shahriar Rokhsaz
IPC分类号： H03D13/00 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/10 , H04L7/033 , H03D3/24 , H03L7/06
CPC分类号： H03L7/10 , H03D13/003 , H03L7/087 , H03L7/0896 , H03L7/091 , H04L7/033
摘要： A high speed phase detector circuit operating at a clock speed equal to one-half an input data rate (i.e. a half-rate clock) provides phase information and transition information from incoming serial data. The high speed phase detector circuit samples the incoming serial data on both the rising edge and falling edge of the half-rate clock to provide equivalent full high speed data rate sampling. The high speed phase detector circuit generates a delay between the phase information and the transition information. The phase information is produced in a first bit period and the transition information is produced in a second bit period relative to the first bit period.
摘要翻译：以等于输入数据速率的二分之一（即半速率时钟）的时钟速度工作的高速相位检测器电路从输入串行数据提供相位信息和转换信息。高速相位检测器电路在半速率时钟的上升沿和下降沿都对输入的串行数据进行采样，以提供等效的全高速数据速率采样。高速相位检测器电路在相位信息和转换信息之间产生延迟。在第一比特周期中产生相位信息，并且以相对于第一比特周期的第二比特周期生成转换信息。

8. 发明申请

US20050134339A1 Method and apparatus for data density-independent phase adjustment in a clock and data recovery system 有权
标题翻译：在时钟和数据恢复系统中用于数据密度无关相位调整的方法和装置
公开(公告)号：US20050134339A1
公开(公告)日：2005-06-23
申请号：US11059739
申请日：2005-02-17
申请人： Ahmed Younis , Firas Abughazaleh
发明人： Ahmed Younis , Firas Abughazaleh
IPC分类号： H03D13/00 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/10 , H04L7/033 , H03K5/01
CPC分类号： H03L7/10 , H03D13/003 , H03L7/087 , H03L7/0896 , H03L7/091 , H04L7/033
摘要： A data density independent clock and data recovery system includes a lock phase adjust charge pump operably coupled to receive phase information and transition information from a phase detector and to produce a current signal, responsive to the phase information and transition information, to a loop filter that converts the current signal to a control voltage signal operably coupled to a voltage controlled oscillator that produces a clock signal to the phase detector based on the control voltage signal. The lock phase adjust charge pump includes a phase charge pump, a transition charge pump, a programmable DC bias current sink, and two programmable offset bias current sinks. The transition charge pump includes a programmable transition current sink. The control logic operates under external control to adjust the currents conducted by the transition charge pump, the programmable DC bias current sink, and the two programmable offset bias current sinks.
摘要翻译：数据密度无关的时钟和数据恢复系统包括锁相调节电荷泵，其可操作地耦合以从相位检测器接收相位信息和转换信息，并且响应于相位信息和转换信息产生电流信号到环路滤波器，将当前信号转换成可操作地耦合到压控振荡器的控制电压信号，该压控振荡器基于控制电压信号产生到相位检测器的时钟信号。锁相调节电荷泵包括相电荷泵，过渡电荷泵，可编程直流偏置电流吸收器和两个可编程偏移电流吸收器。过渡电荷泵包括可编程转换电流吸收器。控制逻辑在外部控制下工作，以调整由过渡电荷泵，可编程直流偏置电流吸收器和两个可编程偏移电流吸收器传导的电流。

9. 发明授权

US07003067B1 High-speed synchronous counters with reduced logic complexity 有权
标题翻译：具有降低逻辑复杂度的高速同步计数器
公开(公告)号：US07003067B1
公开(公告)日：2006-02-21
申请号：US10977305
申请日：2004-10-29
申请人： Ahmed Younis
发明人： Ahmed Younis
IPC分类号： G06M3/00 , H03K23/54
CPC分类号： H03K23/54 , H03K23/548 , H03K23/588
摘要： Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.
摘要翻译：描述了具有减少的组合逻辑的快速同步计数器。在一个实施例中，四位移位寄存器被配置在环中并且用数据模式预设（例如，1000）。然后，寄存器迅速转换成四个独特状态中的任何一个。连接到移位寄存器的组合逻辑将四个唯一状态转换成代表四个状态的二位二进制信号。在一般情况下，根据本实施例的计数器表示使用2N个同步存储元件的N位二进制数。可以组合两个或更多计数器来产生较大的同步计数器。根据另一实施例的升/减计数器连接到多路径延迟线以创建可变延迟电路。延迟电路的切换速度与延迟设置的数量无关。还有利的是，随着延迟粒度的变化，延迟电路在功耗和面积方面线性缩放。

10. 发明授权

US06961402B1 High-speed synchronous counters with reduced logic complexity 有权
标题翻译：具有降低逻辑复杂度的高速同步计数器
公开(公告)号：US06961402B1
公开(公告)日：2005-11-01
申请号：US10977280
申请日：2004-10-29
申请人： Ahmed Younis
发明人： Ahmed Younis
IPC分类号： H03K23/54 , H03K23/58 , H03K21/00
CPC分类号： H03K23/54 , H03K23/548 , H03K23/588
摘要： Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.
摘要翻译：描述了具有减少的组合逻辑的快速同步计数器。在一个实施例中，四位移位寄存器被配置在环中并且用数据模式预设（例如，1000）。然后，寄存器迅速转换成四个独特状态中的任何一个。连接到移位寄存器的组合逻辑将四个唯一状态转换成代表四个状态的二位二进制信号。在一般情况下，根据本实施例的计数器表示使用2N个同步存储元件的N位二进制数。可以组合两个或更多计数器来产生较大的同步计数器。根据另一实施例的升/减计数器连接到多路径延迟线以创建可变延迟电路。延迟电路的切换速度与延迟设置的数量无关。还有利的是，随着延迟粒度的变化，延迟电路在功耗和面积方面线性缩放。

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