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1. 发明授权

US06356160B1 Phase lock loop and automatic gain control circuitry for clock recovery 有权
标题翻译：锁相环和自动增益控制电路，用于时钟恢复
公开(公告)号：US06356160B1
公开(公告)日：2002-03-12
申请号：US09347256
申请日：1999-07-02
申请人： Moises E. Robinson , Bernard L. Grung , Yiqin Chen
发明人： Moises E. Robinson , Bernard L. Grung , Yiqin Chen
IPC分类号： H03L707
CPC分类号： H03L7/093 , H03L7/085 , H03L7/087 , H03L7/14 , H04L7/033
摘要： A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.
摘要翻译：高速数据通信系统包括从通信数据恢复数据和时钟信号的接收机。接收器电路具有双锁相环（PLL）电路。 PLL的精细环路包括提供差分模拟电压输出的相位检测器。跨导电路将差分模拟电压输出转换为低电流模拟输出。跨导电路具有由自动增益调节电路控制的可变增益。 PLL的粗略回路允许快速采集内部振荡器。

2. 发明授权

US06624668B1 Digitally programmable phase-lock loop for high-speed data communications 有权
公开(公告)号：US06624668B1
公开(公告)日：2003-09-23
申请号：US10005736
申请日：2001-11-06
申请人： Moises E. Robinson , Michael J. Gaboury , Bernard L. Grung
发明人： Moises E. Robinson , Michael J. Gaboury , Bernard L. Grung
IPC分类号： H02M1100
CPC分类号： H03L7/18 , H03L7/087 , H03L7/0898 , H03L7/0995 , H03L2207/04 , H04L7/0008 , H04L7/02
摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices. Accordingly, the present inventors devised a digitally programmable phase-lock loop which operates at a frequency selected from a set of two of more frequencies. One such phase-lock loop includes a charge pump, a loop filter, and a voltage-controlled oscillator, all of which are programmable to control the operating frequency of the phase-lock loop and thus devices, such as receivers, transmitters, and transceivers incorporating it. Moreover, the programmability of these three components enables the exemplary embodiment to maintains a constant damping factor and a constant ratio of input frequency to loop bandwidth for each frequency setting, thereby promoting loop stability and rapid settling at each selected frequency.

3. 发明授权

US06462594B1 Digitally programmable phase-lock loop for high-speed data communications 有权
标题翻译：用于高速数据通信的数字可编程锁相环
公开(公告)号：US06462594B1
公开(公告)日：2002-10-08
申请号：US09708695
申请日：2000-11-08
申请人： Moises E. Robinson , Bernard L. Grung
发明人： Moises E. Robinson , Bernard L. Grung
IPC分类号： H03L706
CPC分类号： H03L7/0898 , H03L7/087 , H03L7/0995 , H03L7/18 , H03L2207/04 , H04L7/0008 , H04L7/02
摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices. Accordingly, the present inventors devised a digitally programmable phase-lock loop which operates at a frequency selected from a set of two of more frequencies. One such phase-lock loop includes a charge pump, a loop filter, and a voltage-controlled oscillator, all of which are programmable to control the operating frequency of the phase-lock loop and thus devices, such as receivers, transmitters, and transceivers incorporating it. Moreover, the programmability of these three components enables the exemplary embodiment to maintains a constant damping factor and a constant ratio of input frequency to loop bandwidth for each frequency setting, thereby promoting loop stability and rapid settling at each selected frequency.
摘要翻译：电子设备通常耦合在一起以作为需要在两个或多个设备之间进行数据通信的系统。这些设备中的许多包括通信电路，例如用于此目的的接收器，发射器或收发器。这些通信电路中的典型组件是锁相环，接收器电路中的电路确定接收数据信号中的脉冲的定时，并且在发射器电路中以预定速率对数据进行时钟输出。锁相环的一个问题，因此结合它们的接收器和发射器电路是它们通常被调谐或定制以在特定频率下操作。这意味着通常不能使用具有针对一个频率调谐的锁相环路的接收器或发射器电路在另一个频率上进行通信。在其他频率下无法通信限制了接收机和发射机电路以及其电子设备的有用性。因此，本发明人设计了一种数字可编程锁相环路，其以选自两个以上频率的一组的频率工作。一个这样的锁相环包括电荷泵，环路滤波器和压控振荡器，所有这些都是可编程的，以控制锁相环的工作频率，从而控制诸如接收器，发射器和收发器之类的装置并入它此外，这三个组件的可编程性使得示例性实施例能够为每个频率设置保持恒定的阻尼因子和输入频率与环路带宽的恒定比例，从而提高每个选定频率的环路稳定性和快速建立。

4. 发明授权

US06650720B1 Phase lock loop and transconductance circuit for clock recovery 有权
标题翻译：用于时钟恢复的锁相环和跨导电路
公开(公告)号：US06650720B1
公开(公告)日：2003-11-18
申请号：US09218382
申请日：1998-12-22
申请人： Bernard L. Grung , Moises E. Robinson
发明人： Bernard L. Grung , Moises E. Robinson
IPC分类号： H03D324
CPC分类号： H03L7/085 , H03L7/087 , H03L7/093 , H03L7/14 , H04L7/033
摘要： A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a high impedance output, a small transconductance value and can provide variable gain control. A coarse loop of the PLL allows for frequency acquisition of an internal oscillator.
摘要翻译：高速数据通信系统包括从通信数据恢复数据和时钟信号的接收机。接收器电路具有双锁相环（PLL）电路。 PLL的精细环路包括提供差分模拟电压输出的相位检测器。跨导电路将差分模拟电压输出转换为低电流模拟输出。跨导电路具有高阻抗输出，小跨导值，并可提供可变增益控制。 PLL的粗略回路允许对内部振荡器进行频率采集。

5. 发明授权

US06501339B1 Ring oscillators with improved signal-path matching for high-speed data communications 有权
标题翻译：环形振荡器具有改进的信号路径匹配，用于高速数据通信
公开(公告)号：US06501339B1
公开(公告)日：2002-12-31
申请号：US09927146
申请日：2001-08-10
申请人： Ahmed Younis , Moises E. Robinson , Michael A. Nix , Brian T. Brunn
发明人： Ahmed Younis , Moises E. Robinson , Michael A. Nix , Brian T. Brunn
IPC分类号： H03B524
CPC分类号： H03L7/0995 , H03K3/0315 , H03L7/087 , H03L7/0891 , H03L7/18
摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data from one device to another. Many such devices include a ring oscillator, a circuit that generates one or more oscillating signals using a series of interconnected delay circuits. One problem with conventional ring oscillators concerns differences in the signal paths between the delay circuits. Accordingly, the present inventors devised several oscillators having unique layouts, which reduce differences in the signal paths between delay circuits. One exemplary oscillator includes a sequence of delay circuits having input-output connections between at least two pairs of non-adjacent delay circuits. Another exemplary oscillator provides two groups of delay circuits with a bus between the two groups, intercoupling the circuits. And, another exemplary oscillator arranges three or more delay circuits to form a closed loop. Applications for these oscillators include not only receivers, transmitters, and transceivers, but also programmable integrated circuits, electronic devices, and systems.
摘要翻译：电子设备通常耦合在一起以作为需要从一个设备到另一个设备的数据通信的系统进行操作。许多这样的设备包括环形振荡器，使用一系列互连的延迟电路产生一个或多个振荡信号的电路。常规环形振荡器的一个问题涉及延迟电路之间的信号路径的差异。因此，本发明人设计了具有独特布局的几个振荡器，其减小延迟电路之间的信号路径的差异。一个示例性振荡器包括在至少两对非相邻延迟电路之间具有输入 - 输出连接的延迟电路序列。另一个示例性振荡器提供两组延迟电路，其中两组之间的总线相互耦合。并且，另一示例性振荡器布置三个或更多个延迟电路以形成闭环。这些振荡器的应用不仅包括接收器，发射器和收发器，还包括可编程集成电路，电子设备和系统。

6. 发明授权

US07224760B1 High-speed wide bandwidth data detection circuit 有权
标题翻译：高速宽带数据检测电路
公开(公告)号：US07224760B1
公开(公告)日：2007-05-29
申请号：US10421512
申请日：2003-04-22
申请人： Shahriar Rokhsaz , Moises E. Robinson , Ahmed Younis , Brian T. Brunn
发明人： Shahriar Rokhsaz , Moises E. Robinson , Ahmed Younis , Brian T. Brunn
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H03D13/003 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/10
摘要： A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.
摘要翻译：高速，宽带宽数据检测电路包括相位检测模块，数据检测模块，环路滤波器和压控振荡器。相位检测模块可操作地耦合以基于对输入数据流和恢复的时钟之间的差异的当前模式数学操作产生受控电流。相位检测模块执行当前模式的数学操作并产生当前域中的受控电流。数据检测模块可操作地耦合以基于输入数据流和恢复的时钟产生检测到的数据。环路滤波器可操作地耦合以将受控电流转换成受控电压。压控振荡器可操作地耦合以将控制电压转换成恢复的时钟。

7. 发明授权

US06809676B1 Method and system for VCO-based analog-to-digital conversion (ADC) 有权
标题翻译：基于VCO的模数转换（ADC）的方法和系统
公开(公告)号：US06809676B1
公开(公告)日：2004-10-26
申请号：US10224977
申请日：2002-08-20
申请人： Ahmed Younis , Marwan M. Hassoun , Moises E. Robinson
发明人： Ahmed Younis , Marwan M. Hassoun , Moises E. Robinson
IPC分类号： H03M160
CPC分类号： H03M1/60
摘要： A VCO (110) can be configured to convert an analog input signal (105) to a digital output signal (125). In accordance with the inventive arrangements, the VCO can convert the analog input signal to at least one intermediate signal (130) having a frequency dependent on the analog input signal. A frequency detector (115) can be configured to determine a frequency of at least one intermediate signal. Subsequently, a mapping circuit (120) can be configured to map the determined frequency of the at least one intermediate signal to an output value representing the digital output signal (125).
摘要翻译： VCO（110）可以被配置为将模拟输入信号（105）转换成数字输出信号（125）。根据本发明的结构，VCO可以将模拟输入信号转换成具有取决于模拟输入信号的频率的至少一个中间信号（130）。频率检测器（115）可被配置为确定至少一个中间信号的频率。随后，映射电路（120）可以被配置为将所确定的至少一个中间信号的频率映射到表示数字输出信号（125）的输出值。

8. 发明授权

US09312686B2 High voltage protection circuit for non-tolerant integrated circuit 有权
标题翻译：高耐压集成电路用高压保护电路
公开(公告)号：US09312686B2
公开(公告)日：2016-04-12
申请号：US13339444
申请日：2011-12-29
申请人： Anil Kumar , Michael A. Nix , Moises E. Robinson , Carlin D. Cabler
发明人： Anil Kumar , Michael A. Nix , Moises E. Robinson , Carlin D. Cabler
IPC分类号： H02H9/00 , H02H7/20 , H02H9/04
CPC分类号： H02H7/20 , H02H9/041
摘要： A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.
摘要翻译：本文描述了一种用于非容错集成电路的高压保护电路。不容忍的集成电路可以是可以暴露于诸如外部电路，设备或电源的高电压源的掉电集成电路或低电压容限集成电路。高压保护电路包括限制晶体管电路，控制晶体管电路和隔离晶体管电路。限制晶体管电路限制或保持信号凸起处的电压小于可能损坏电路的电压。隔离晶体管电路将输入/输出信号电路与正常保护电路断开。限制晶体管电路和隔离晶体管电路均由控制晶体管电路控制，并且响应于电源电压关断。

9. 发明申请

US20130170078A1 HIGH VOLTAGE PROTECTION CIRCUIT FOR NON-TOLERANT INTEGRATED CIRCUIT 有权
标题翻译：用于非易失性集成电路的高压保护电路
公开(公告)号：US20130170078A1
公开(公告)日：2013-07-04
申请号：US13339444
申请日：2011-12-29
申请人： Anil Kumar , Michael A. Nix , Moises E. Robinson , Carlin D. Cabler
发明人： Anil Kumar , Michael A. Nix , Moises E. Robinson , Carlin D. Cabler
IPC分类号： H02H7/20
CPC分类号： H02H7/20 , H02H9/041
摘要： A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.
摘要翻译：本文描述了一种用于非容错集成电路的高压保护电路。不容忍的集成电路可以是可以暴露于诸如外部电路，设备或电源的高电压源的掉电集成电路或低电压容限集成电路。高压保护电路包括限制晶体管电路，控制晶体管电路和隔离晶体管电路。限制晶体管电路限制或保持信号凸起处的电压小于可能损坏电路的电压。隔离晶体管电路将输入/输出信号电路与正常保护电路断开。限制晶体管电路和隔离晶体管电路均由控制晶体管电路控制，并且响应于电源电压关断。

10. 发明授权

US07499513B1 Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit 有权
标题翻译：用于在集成电路中提供频率合成和相位对准的方法和装置
公开(公告)号：US07499513B1
公开(公告)日：2009-03-03
申请号：US11049329
申请日：2005-02-02
申请人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
发明人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： G06F1/10 , H03L7/07 , H03L7/0891 , H03L7/095 , H03L7/183
摘要： According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.
摘要翻译：根据特定示例性实施例，集成电路包括一个或多个串行数据发送器。每个这样的数据发射器被布置成在集成电路的相应数据输出端口上发送数据，其中用于至少一个数据发射器的相应数据输出端口专用于发送用于对相应目标电路计时的周期性数据。在涉及反馈的其他具体实施例中，在可编程逻辑器件（PLD）的功能块中实现了锁相环（PLL）信号控制和/或延迟锁定环（DLL）信号控制。 PLD响应于源时钟并且包括可配置逻辑阵列，其包括可配置逻辑块和可配置路由块，并且用于至少一个数据发射器的相应数据输出端口提供相应的目标时钟。

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