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1. 发明授权

US06675327B1 Communications system including lower rate parallel electronics with skew compensation and associated methods 有权
标题翻译：通信系统包括具有偏斜补偿的低速并行电路和相关方法
公开(公告)号：US06675327B1
公开(公告)日：2004-01-06
申请号：US09460165
申请日：1999-12-13
申请人： Mohammad S. Mobin , Michael S. Shaffer , Himanshu Mahendra Thaker , Charles Albert Webb, III , Lesley Jen-Yuan Wu
发明人： Mohammad S. Mobin , Michael S. Shaffer , Himanshu Mahendra Thaker , Charles Albert Webb, III , Lesley Jen-Yuan Wu
IPC分类号： G11B500
CPC分类号： H04L1/0061 , H04J3/0626 , H04L25/4904
摘要： A communications system includes a first device comprising a plurality of electrical-to-transmission medium converters, and a second device comprising a plurality of transmission medium-to-electrical converters to be connected to respective ones of the electrical-to-transmission medium converters via at least one transmission medium and defining parallel communications channels between the first and second devices, and wherein deskewing is provided. More particularly, the first device may include a string-based framing coder for determining and appending a string-based framing code to each information symbol string of information symbol strings to be transmitted in parallel over respective parallel communications channels. Each string-based framing code is based upon at least some of the information symbols in the respective information symbol string. The second device preferably comprises a deskewer for aligning received information symbol strings based upon the string-based framing codes. The symbols may be binary bits, and the string-based codes may be CRC codes.
摘要翻译：通信系统包括包括多个电传输介质转换器的第一设备和包括多个传输介质到电转换器的第二设备，所述多个传输介质到电转换器经由至少一个传输介质并且在第一和第二设备之间定义并行通信信道，并且其中提供了去歪斜。更具体地，第一设备可以包括基于串的成帧编码器，用于确定并将基于字符串的成帧代码附加到要在各个并行通信信道上并行发送的信息符号串的每个信息符号串。每个基于字符串的成帧代码基于相应信息符号串中的至少一些信息符号。第二装置优选地包括用于基于基于字符串的成帧代码来对准所接收的信息符号串的偏台。符号可以是二进制位，并且基于字符串的代码可以是CRC码。

2. 发明授权

US08284882B2 Methods and apparatus for qualification of update of clock recovery and equalization 有权
标题翻译：用于更新时钟恢复和均衡的方法和装置
公开(公告)号：US08284882B2
公开(公告)日：2012-10-09
申请号：US12491760
申请日：2009-06-25
申请人： Gregory A. Kleese , Mohammad S. Mobin , Kenneth W. Paist
发明人： Gregory A. Kleese , Mohammad S. Mobin , Kenneth W. Paist
IPC分类号： H04L7/00
CPC分类号： H04L25/03006 , H04L7/0058 , H04L25/03057 , H04L2025/03535 , H04L2025/03732
摘要： Methods and apparatus are provided for CDR and equalization update qualification. A block of received data comprising a plurality of multiple tone patterns is processed. Equalization adaptation and/or updates to a timing recovery process can be selectively disabled if one or more of the multiple tone patterns exceed a corresponding predefined threshold.
摘要翻译：为CDR和均衡更新资格提供了方法和装置。处理包括多个多个色调图案的接收数据块。如果多个音调模式中的一个或多个超过相应的预定义阈值，则可以选择性地禁用对定时恢复过程的均衡适配和/或更新。

3. 发明授权

US08219344B2 Method and apparatus for digital VCDL startup 失效
标题翻译：数字VCDL启动的方法和装置
公开(公告)号：US08219344B2
公开(公告)日：2012-07-10
申请号：US12789544
申请日：2010-05-28
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译：提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。可以使用所确定的控制信号来开始压控延迟环路。可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。

4. 发明申请

US20100128828A1 METHODS AND APPARATUS FOR ADAPTING ONE OR MORE EQUALIZATION PARAMETERS BY REDUCING GROUP DELAY SPREAD 有权
标题翻译：通过减少组延迟扩展来适应一个或多个均衡参数的方法和装置
公开(公告)号：US20100128828A1
公开(公告)日：2010-05-27
申请号：US12323155
申请日：2008-11-25
申请人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith
发明人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith
IPC分类号： H04B1/10
CPC分类号： H04L25/03006 , H04L2025/0349
摘要： Methods and apparatus are provided for adapting one or more equalization parameters in a communications system by reducing group delay spread. According to one aspect of the invention, one or more equalization parameters in a communications system are adapted by detecting one or more predefined run length patterns in a received signal, such as a plurality of consecutive same-valued bits; evaluating a transition latch value for each of the detected predefined run length patterns, wherein the transition latch value provides an indication of whether the received signal is under-equalized or over-equalized; and adjusting the one or more equalization parameters of the communications system based on the evaluation of the transition latch value. The adjusted equalization parameters may be employed to equalize intersymbol interference. A data eye monitor can be employed to evaluate the transition latch value.
摘要翻译：提供了用于通过减少组延迟扩展来调整通信系统中的一个或多个均衡参数的方法和装置。根据本发明的一个方面，通信系统中的一个或多个均衡参数通过检测接收信号中的一个或多个预定义的游程长度模式来适配，诸如多个连续的同值比特; 评估所检测到的预定游程长度模式中的每一个的转换锁存值，其中所述转换锁存值提供所述接收信号是否欠均衡或过均衡的指示; 以及基于所述转换锁存器值的评估来调整所述通信系统的一个或多个均衡参数。可以采用经调整的均衡参数来均衡码间干扰。数据眼监视器可用于评估转换锁存值。

5. 发明授权

US07693088B2 Method and apparatus for data rate detection using a data eye monitor 有权
标题翻译：使用数据眼监视器进行数据速率检测的方法和装置
公开(公告)号：US07693088B2
公开(公告)日：2010-04-06
申请号：US11686144
申请日：2007-03-14
申请人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H04L12/26 , H04J3/06 , H04B17/00
CPC分类号： H04L25/0262
摘要： Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.
摘要翻译：提供了使用数据眼监视器进行数据速率检测的方法和装置。数据速率是包括基本速率和基本速率的一个或多个除以N倍数的多个数据速率之一，其中N是整数。通过对接收到的信号进行采样来检测接收信号的数据速率; 比较与所接收的信号相关联的多个全速率数据眼睛的样本，以确定是否存在至少两个预定样本之间的不匹配; 以及通过基于预定标准评估比较来检测数据速率。可以通过异或（XOR）逻辑门对给定速率的至少两个相邻数据眼的样本执行比较。

6. 发明申请

US20100054383A1 METHODS AND APPARATUS FOR GENERATING EARLY OR LATE SAMPLING CLOCKS FOR CDR DATA RECOVERY 有权
标题翻译：用于生成CDR数据恢复的早期或最后采样时钟的方法和装置
公开(公告)号：US20100054383A1
公开(公告)日：2010-03-04
申请号：US12199904
申请日：2008-08-28
申请人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith , Paul H. Tracy , William B. Wilson
发明人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith , Paul H. Tracy , William B. Wilson
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.
摘要翻译：提供了用于CDR数据采样的时钟相位发生器的方法和装置，其相对于理想的转换和采样点产生早和/或晚的采样时钟。通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生早期采样时钟; 以及延迟所述转换时钟信号中的至少一个以产生一个或多个早期时钟信号。通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生延迟采样时钟; 以及延迟所述数据采样时钟信号中的至少一个以产生一个或多个后期时钟信号。早期的时钟信号可以用于例如基于阈值的判决反馈均衡器中。后期时钟信号可以用于例如经典的判决反馈均衡器中。

7. 发明申请

US20090219978A1 Methods And Apparatus For Adaptive Link Partner Transmitter Equalization 有权
标题翻译：自适应链路伙伴发射机均衡的方法和装置
公开(公告)号：US20090219978A1
公开(公告)日：2009-09-03
申请号：US12040575
申请日：2008-02-29
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H04B1/38
CPC分类号： H04L25/03006 , H04L25/03343 , H04L2025/0377 , H04L2025/03808
摘要： Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one ox more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern. Noise margins and jitters margins for the channel can optionally be improved.
摘要翻译：为自适应链路伙伴发射机均衡提供了方法和装置。根据本发明的一个方面，本地收发器通过在所述链路伙伴和所述本地收发器之间的信道上接收训练帧来适配链路伙伴的一个更多的均衡参数，其中所述训练帧由预定的训练模式组成; 调整所述链路伙伴的一个或多个均衡参数; 以及基于所述预定训练模式是否由所述本地收发器适当地接收来确定所述信道的均衡是否满足一个或多个预定标准。所述预定训练模式可以是诸如PN11模式的伪随机模式。通道的噪声余量和抖动余量可以任意改进。

8. 发明授权

US07570708B2 Serdes auto calibration and load balancing 有权
标题翻译： Serdes自动校准和负载平衡
公开(公告)号：US07570708B2
公开(公告)日：2009-08-04
申请号：US11046669
申请日：2005-01-31
申请人： Donald Laturell , Gregory Sheets , Lane Smith , Mohammad S. Mobin
发明人： Donald Laturell , Gregory Sheets , Lane Smith , Mohammad S. Mobin
IPC分类号： H04K1/02
CPC分类号： H04L1/205
摘要： The present invention is used to automatically calibrate a SERDES device by utilizing information provided in the eye diagram of the received signal. In particular, the invention mitigates the components of determininistic jitter, such as ISI and frequency distortion. To achieve this goal, the invention enables the receive side of the SERDES to evaluate the quality of the eye received using a cost function. The invention calculates the cost function associated with the received data and then uses this information to effect an auto calibration of the SERDES device.
摘要翻译：本发明用于通过利用在接收信号的眼图中提供的信息来自动校准SERDES设备。特别地，本发明减轻了确定性抖动的组成部分，例如ISI和频率失真。为了实现这个目标，本发明使得SERDES的接收端能够使用成本函数评估所接收的眼睛的质量。本发明计算与接收到的数据相关联的成本函数，然后使用该信息来实现SERDES设备的自动校准。

9. 发明申请

US20090168862A1 Methods and Apparatus for Detecting and Decoding Adaptive Equalization Training Frames 有权
标题翻译：用于检测和解码自适应均衡训练帧的方法和装置
公开(公告)号：US20090168862A1
公开(公告)日：2009-07-02
申请号：US11967463
申请日：2007-12-31
申请人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
发明人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H04L27/01
CPC分类号： H04L27/01 , H04L7/0066 , H04L7/0083 , H04L25/4904
摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
摘要翻译：提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

10. 发明申请

US20090110045A1 METHOD AND APPARATUS FOR RATE-DEPENDENT EQUALIZATION 失效
标题翻译：用于速率依赖均衡的方法和装置
公开(公告)号：US20090110045A1
公开(公告)日：2009-04-30
申请号：US11930780
申请日：2007-10-31
申请人： Pervez M. Aziz , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Pervez M. Aziz , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L25/0262 , H04L2025/03547
摘要： Methods and apparatus are provided fox equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
摘要翻译：提供了均衡接收信号的方法和装置。接收到的信号通过确定接收信号的数据速率来均衡; 获得与所确定的数据速率相关联的一个或多个均衡参数; 以及使用所获得的一个或多个均衡参数来均衡所接收的信号。均衡参数可以包括例如增益参数，高通滤波器的零控制和在均衡步骤期间使用的一个或多个锁存器的一个或多个阈值设置中的一个或多个，诸如数据锁存器或转换锁存器（或都）。

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