专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07693088B2 Method and apparatus for data rate detection using a data eye monitor 有权
标题翻译：使用数据眼监视器进行数据速率检测的方法和装置
公开(公告)号：US07693088B2
公开(公告)日：2010-04-06
申请号：US11686144
申请日：2007-03-14
申请人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H04L12/26 , H04J3/06 , H04B17/00
CPC分类号： H04L25/0262
摘要： Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.
摘要翻译：提供了使用数据眼监视器进行数据速率检测的方法和装置。数据速率是包括基本速率和基本速率的一个或多个除以N倍数的多个数据速率之一，其中N是整数。通过对接收到的信号进行采样来检测接收信号的数据速率; 比较与所接收的信号相关联的多个全速率数据眼睛的样本，以确定是否存在至少两个预定样本之间的不匹配; 以及通过基于预定标准评估比较来检测数据速率。可以通过异或（XOR）逻辑门对给定速率的至少两个相邻数据眼的样本执行比较。

2. 发明申请

US20080225734A1 METHOD AND APPARATUS FOR DATA RATE DETECTION USING A DATA EYE MONITOR 有权
标题翻译：使用数据眼监视器进行数据速率检测的方法和装置
公开(公告)号：US20080225734A1
公开(公告)日：2008-09-18
申请号：US11686144
申请日：2007-03-14
申请人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H04J1/16
CPC分类号： H04L25/0262
摘要： Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.
摘要翻译：提供了使用数据眼监视器进行数据速率检测的方法和装置。数据速率是包括基本速率和基本速率的一个或多个除以N倍数的多个数据速率之一，其中N是整数。通过对接收到的信号进行采样来检测接收信号的数据速率; 比较与所接收的信号相关联的多个全速率数据眼睛的样本，以确定是否存在至少两个预定样本之间的不匹配; 以及通过基于预定标准评估比较来检测数据速率。可以通过异或（XOR）逻辑门对给定速率的至少两个相邻数据眼的样本执行比较。

3. 发明授权

US08219344B2 Method and apparatus for digital VCDL startup 失效
标题翻译：数字VCDL启动的方法和装置
公开(公告)号：US08219344B2
公开(公告)日：2012-07-10
申请号：US12789544
申请日：2010-05-28
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译：提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。可以使用所确定的控制信号来开始压控延迟环路。可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。

4. 发明申请

US20090219978A1 Methods And Apparatus For Adaptive Link Partner Transmitter Equalization 有权
标题翻译：自适应链路伙伴发射机均衡的方法和装置
公开(公告)号：US20090219978A1
公开(公告)日：2009-09-03
申请号：US12040575
申请日：2008-02-29
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H04B1/38
CPC分类号： H04L25/03006 , H04L25/03343 , H04L2025/0377 , H04L2025/03808
摘要： Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one ox more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern. Noise margins and jitters margins for the channel can optionally be improved.
摘要翻译：为自适应链路伙伴发射机均衡提供了方法和装置。根据本发明的一个方面，本地收发器通过在所述链路伙伴和所述本地收发器之间的信道上接收训练帧来适配链路伙伴的一个更多的均衡参数，其中所述训练帧由预定的训练模式组成; 调整所述链路伙伴的一个或多个均衡参数; 以及基于所述预定训练模式是否由所述本地收发器适当地接收来确定所述信道的均衡是否满足一个或多个预定标准。所述预定训练模式可以是诸如PN11模式的伪随机模式。通道的噪声余量和抖动余量可以任意改进。

5. 发明申请

US20090110045A1 METHOD AND APPARATUS FOR RATE-DEPENDENT EQUALIZATION 失效
标题翻译：用于速率依赖均衡的方法和装置
公开(公告)号：US20090110045A1
公开(公告)日：2009-04-30
申请号：US11930780
申请日：2007-10-31
申请人： Pervez M. Aziz , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Pervez M. Aziz , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L25/0262 , H04L2025/03547
摘要： Methods and apparatus are provided fox equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
摘要翻译：提供了均衡接收信号的方法和装置。接收到的信号通过确定接收信号的数据速率来均衡; 获得与所确定的数据速率相关联的一个或多个均衡参数; 以及使用所获得的一个或多个均衡参数来均衡所接收的信号。均衡参数可以包括例如增益参数，高通滤波器的零控制和在均衡步骤期间使用的一个或多个锁存器的一个或多个阈值设置中的一个或多个，诸如数据锁存器或转换锁存器（或都）。

6. 发明授权

US08040984B2 Methods and apparatus for improved jitter tolerance in an SFP limit amplified signal 失效
标题翻译：用于改善SFP限幅放大信号中抖动容限的方法和装置
公开(公告)号：US08040984B2
公开(公告)日：2011-10-18
申请号：US11967602
申请日：2007-12-31
申请人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
发明人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
IPC分类号： H04L25/08 , H04L7/10 , H04L7/00
CPC分类号： H04B10/6972
摘要： Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.
摘要翻译：提供了用于改善SFP限幅放大信号中的抖动容限的方法和装置。在通信接收机中通过将接收到的信号施加到SFP限幅放大器来提高抖动容差; 并将SFP限幅放大器的输出施加到低通滤波器以提高抖动容限。低通滤波器可选择地将可编程量的衰减应用于输出的高频分量。低通滤波器转换速率控制（即旋转）接收信号的数据眼表示，以沿着时间轴增加数据眼睛表示。可以通过将低通滤波器的输出施加到全通滤波器来可选地改善接收信号的噪声容限。压摆率控制器可以评估数据眼统计量，以确定低通滤波器的设置。

7. 发明申请

US20090167379A1 Method and Apparatus for Digital VCDL Startup 有权
标题翻译：数字VCDL启动方法与装置
公开(公告)号：US20090167379A1
公开(公告)日：2009-07-02
申请号：US11967619
申请日：2007-12-31
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided fox improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The control signal can be, for example, a delay control current or a delay control voltage. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination. The determined control signal can optionally be stored in a table for each of the plurality of PVT combinations
摘要翻译：提供了具有注入时钟和返回时钟的电压控制延迟回路的改进的启动方法和装置。通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。控制信号可以是例如延迟控制电流或延迟控制电压。可以使用所确定的控制信号来开始压控延迟环路。可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。所确定的控制信号可以可选地存储在用于多个PVT组合中的每一个的表中

8. 发明授权

US07606302B2 Method and apparatus for non-linear decision-feedback equalization in the presence of asymmetric channel 有权
标题翻译：在存在非对称信道的情况下进行非线性判决反馈均衡的方法和装置
公开(公告)号：US07606302B2
公开(公告)日：2009-10-20
申请号：US11541379
申请日：2006-09-29
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04B10/695
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization in the presence of a non-linear channel. A latch employed by a decision-feedback equalizer is positioned by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; determining a threshold position of the latch based on the samples; and transforming the determined position to address the non-linearity of the channel. For example, a non-linear mapping table can map measured threshold values to transformed threshold values based on distance.
摘要翻译：提供了用于在存在非线性通道的情况下确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。由判决反馈均衡器采用的锁存器通过约束输入数据来定位，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 基于所述样本确定所述锁存器的阈值位置; 并且变换确定的位置以解决信道的非线性。例如，非线性映射表可以将测量的阈值映射到基于距离的变换的阈值。

9. 发明授权

US08320439B2 Methods and apparatus for adaptive link partner transmitter equalization 有权
标题翻译：自适应链路伙伴发射机均衡的方法和装置
公开(公告)号：US08320439B2
公开(公告)日：2012-11-27
申请号：US12040575
申请日：2008-02-29
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03H7/30
CPC分类号： H04L25/03006 , H04L25/03343 , H04L2025/0377 , H04L2025/03808
摘要： Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.
摘要翻译：为自适应链路伙伴发射机均衡提供了方法和装置。根据本发明的一个方面，本地收发器通过在链路伙伴和本地收发信机之间的信道上接收训练帧来适配链路伙伴的一个或多个均衡参数，其中训练帧由预定义的训练模式组成; 调整所述链路伙伴的一个或多个均衡参数; 以及基于所述本地收发器是否适当地接收了所述预定训练模式，确定所述信道的均衡是否满足一个或多个预定标准。预定义的训练模式可以是伪随机模式，例如PN11模式，可以可选地提高通道的噪声余量和抖动余量。

10. 发明申请

US20100237915A1 METHOD AND APPARATUS FOR DIGITAL VCDL STARTUP 失效
标题翻译：数字VCDL启动的方法与装置
公开(公告)号：US20100237915A1
公开(公告)日：2010-09-23
申请号：US12789544
申请日：2010-05-28
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the deter wined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译：提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。电压控制延迟环可以使用阻尼控制信号启动。可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式