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1. 发明授权

US08130534B2 System and method to read and write data a magnetic tunnel junction element 有权
标题翻译：在磁性隧道结元件上读取和写入数据的系统和方法
公开(公告)号：US08130534B2
公开(公告)日：2012-03-06
申请号：US12350304
申请日：2009-01-08
申请人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
发明人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1657 , G11C11/1659 , G11C11/1673
摘要： A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.
摘要翻译：公开了一种在磁随机存取存储器中读取和写入数据的系统和方法。在特定实施例中，器件包括自旋转移转矩磁隧道结（STT-MTJ）元件和具有耦合到STT-MTJ元件的第一栅极和第二栅极的晶体管。

2. 发明申请

US20100172173A1 System And Method To Read And Write Data A Magnetic Tunnel Junction Element 有权
标题翻译：在磁性隧道结元件上读取和写入数据的系统和方法
公开(公告)号：US20100172173A1
公开(公告)日：2010-07-08
申请号：US12350304
申请日：2009-01-08
申请人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
发明人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
IPC分类号： G11C11/02 , G11C11/14 , G11C11/416
CPC分类号： G11C11/1675 , G11C11/1657 , G11C11/1659 , G11C11/1673
摘要： A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.
摘要翻译：公开了一种在磁随机存取存储器中读取和写入数据的系统和方法。在特定实施例中，器件包括自旋转移转矩磁隧道结（STT-MTJ）元件和具有耦合到STT-MTJ元件的第一栅极和第二栅极的晶体管。

3. 发明申请

US20100061144A1 Memory Device for Resistance-Based Memory Applications 有权
标题翻译：用于基于电阻的存储器应用的存储器件
公开(公告)号：US20100061144A1
公开(公告)日：2010-03-11
申请号：US12206933
申请日：2008-09-09
申请人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
发明人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/1673
摘要： In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.
摘要翻译：在特定实施例中，公开了一种存储器件，其包括存储单元，该存储单元包括耦合到存取晶体管的基于电阻的存储元件。存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。存储器件还包括第一放大器，其被配置为将存储器单元耦合到大于电压限制的电源电压，以基于通过存储器单元的电流来产生数据信号。第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管。钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

4. 发明授权

US08228714B2 Memory device for resistance-based memory applications 有权
标题翻译：用于基于电阻的存储器应用的存储器件
公开(公告)号：US08228714B2
公开(公告)日：2012-07-24
申请号：US12206933
申请日：2008-09-09
申请人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
发明人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
IPC分类号： G11C11/00
CPC分类号： G11C11/1673
摘要： In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.
摘要翻译：在特定实施例中，公开了一种存储器件，其包括存储单元，该存储单元包括耦合到存取晶体管的基于电阻的存储元件。存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。存储器件还包括第一放大器，其被配置为将存储器单元耦合到大于电压限制的电源电压，以基于通过存储器单元的电流来产生数据信号。第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管。钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

5. 发明授权

US07672175B2 System and method of selectively applying negative voltage to wordlines during memory device read operation 有权
标题翻译：在存储器件读取操作期间选择性地向字线施加负电压的系统和方法
公开(公告)号：US07672175B2
公开(公告)日：2010-03-02
申请号：US11972696
申请日：2008-01-11
申请人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma
发明人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma
IPC分类号： G11C7/22
CPC分类号： G11C8/08 , G11C11/1673
摘要： Systems and methods of selectively applying negative voltage to word lines during memory device read operation are disclosed. In an embodiment, a memory device includes a word line logic circuit coupled to a plurality of word lines and adapted to selectively apply a positive voltage to a selected word line coupled to a selected memory cell that includes a magnetic tunnel junction (MTJ) device and to apply a negative voltage to unselected word lines.
摘要翻译：公开了在存储器件读取操作期间选择性地向字线施加负电压的系统和方法。在一个实施例中，存储器件包括字线逻辑电路，其耦合到多个字线并且适于选择性地将正电压施加到与包括磁性隧道结（MTJ）器件的选定存储器单元耦合的所选择的字线，对未选择的字线施加负电压。

6. 发明申请

US20090180315A1 System and Method of Selectively Applying Negative Voltage to Wordlines During Memory Device Read Operation 有权
标题翻译：在存储器读取操作期间选择性地对字线施加负电压的系统和方法
公开(公告)号：US20090180315A1
公开(公告)日：2009-07-16
申请号：US11972696
申请日：2008-01-11
申请人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma
发明人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma
IPC分类号： G11C11/14
CPC分类号： G11C8/08 , G11C11/1673
摘要： Systems and methods of selectively applying negative voltage to word lines during memory device read operation are disclosed. In an embodiment, a memory device includes a word line logic circuit coupled to a plurality of word lines and adapted to selectively apply a positive voltage to a selected word line coupled to a selected memory cell that includes a magnetic tunnel junction (MTJ) device and to apply a negative voltage to unselected word lines.
摘要翻译：公开了在存储器件读取操作期间选择性地向字线施加负电压的系统和方法。在一个实施例中，存储器件包括字线逻辑电路，其耦合到多个字线并且适于选择性地将正电压施加到与包括磁性隧道结（MTJ）器件的所选存储器单元耦合的所选择的字线，对未选择的字线施加负电压。

7. 发明申请

US20100142303A1 Digitally-Controllable Delay for Sense Amplifier 有权
标题翻译：检测放大器的数字可控延迟
公开(公告)号：US20100142303A1
公开(公告)日：2010-06-10
申请号：US12329941
申请日：2008-12-08
申请人： Dongkyu Park , Anosh B. Davierwalla , Cheng Zhong , Mohamed Hassan Soliman Abu-Rahma , Sei Seung Yoon
发明人： Dongkyu Park , Anosh B. Davierwalla , Cheng Zhong , Mohamed Hassan Soliman Abu-Rahma , Sei Seung Yoon
IPC分类号： G11C7/08 , G11C11/02
CPC分类号： G11C7/22 , G11C7/06 , G11C11/1673 , G11C11/1693 , G11C2207/065 , G11C2207/2281
摘要： Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit. The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal from the digitally-controllable amplifier via the logic circuit.
摘要翻译：公开了在读取磁随机存取存储器（MRAM）装置中插入可选延迟的电路，装置和方法。在特定实施例中，电路包括具有第一输入，第二输入和使能输入的读出放大器。还提供耦合到基于磁阻的存储器单元的输出的第一放大器和耦合到单元的参考输出的第二放大器。电路还包括耦合到跟踪电路单元的数字可控放大器。跟踪电路单元包括与基于磁阻的存储器的单元相似的至少一个元件。读出放大器的第一输入耦合到第一放大器，读出放大器的第二输入耦合到第二放大器，并且使能输入经由逻辑电路耦合到第三数字可控放大器。一旦读出放大器经由逻辑电路接收到来自数字可控放大器的使能信号，读出放大器可以基于从基于磁阻的存储单元和参考单元的输出接收的放大值产生输出值。

8. 发明授权

US07936590B2 Digitally-controllable delay for sense amplifier 有权
标题翻译：读数放大器的数字可控延时
公开(公告)号：US07936590B2
公开(公告)日：2011-05-03
申请号：US12329941
申请日：2008-12-08
申请人： Dongkyu Park , Anosh B. Davierwalla , Cheng Zhong , Mohamed Hassan Soliman Abu-Rahma , Sei Seung Yoon
发明人： Dongkyu Park , Anosh B. Davierwalla , Cheng Zhong , Mohamed Hassan Soliman Abu-Rahma , Sei Seung Yoon
IPC分类号： G11C11/00
CPC分类号： G11C7/22 , G11C7/06 , G11C11/1673 , G11C11/1693 , G11C2207/065 , G11C2207/2281
摘要： Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit. The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal from the digitally-controllable amplifier via the logic circuit.
摘要翻译：公开了在读取磁随机存取存储器（MRAM）装置中插入可选延迟的电路，装置和方法。在特定实施例中，电路包括具有第一输入，第二输入和使能输入的读出放大器。还提供耦合到基于磁阻的存储器单元的输出的第一放大器和耦合到单元的参考输出的第二放大器。电路还包括耦合到跟踪电路单元的数字可控放大器。跟踪电路单元包括与基于磁阻的存储器的单元相似的至少一个元件。读出放大器的第一输入耦合到第一放大器，读出放大器的第二输入耦合到第二放大器，并且使能输入经由逻辑电路耦合到第三数字可控放大器。一旦读出放大器经由逻辑电路接收到来自数字可控放大器的使能信号，读出放大器可以基于从基于磁阻的存储单元和参考单元的输出接收的放大值产生输出值。

9. 发明授权

US07995378B2 MRAM device with shared source line 有权
标题翻译：具有共享源线的MRAM设备
公开(公告)号：US07995378B2
公开(公告)日：2011-08-09
申请号：US11959515
申请日：2007-12-19
申请人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed H. Abu-Rahma
发明人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed H. Abu-Rahma
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673
摘要： In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell.
摘要翻译：在特定实施例中，存储器设备包括第一存储器单元和第二存储器单元。存储器件还包括与第一存储器单元相关联的第一位线和与第二存储器单元相关联的第二位线。存储器件还包括耦合到第一存储器单元并耦合到第二存储器单元的源极线。

10. 发明申请

US20090161413A1 MRAM Device with Shared Source Line 有权
标题翻译：具有共享源线的MRAM设备
公开(公告)号：US20090161413A1
公开(公告)日：2009-06-25
申请号：US11959515
申请日：2007-12-19
申请人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed H. Abu-Rahma
发明人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed H. Abu-Rahma
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673
摘要： In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell.
摘要翻译：在特定实施例中，存储器设备包括第一存储器单元和第二存储器单元。存储器件还包括与第一存储器单元相关联的第一位线和与第二存储器单元相关联的第二位线。存储器件还包括耦合到第一存储器单元并耦合到第二存储器单元的源极线。

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