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1. 发明授权

US08130534B2 System and method to read and write data a magnetic tunnel junction element 有权
标题翻译：在磁性隧道结元件上读取和写入数据的系统和方法
公开(公告)号：US08130534B2
公开(公告)日：2012-03-06
申请号：US12350304
申请日：2009-01-08
申请人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
发明人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1657 , G11C11/1659 , G11C11/1673
摘要： A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.
摘要翻译：公开了一种在磁随机存取存储器中读取和写入数据的系统和方法。在特定实施例中，器件包括自旋转移转矩磁隧道结（STT-MTJ）元件和具有耦合到STT-MTJ元件的第一栅极和第二栅极的晶体管。

2. 发明申请

US20100172173A1 System And Method To Read And Write Data A Magnetic Tunnel Junction Element 有权
标题翻译：在磁性隧道结元件上读取和写入数据的系统和方法
公开(公告)号：US20100172173A1
公开(公告)日：2010-07-08
申请号：US12350304
申请日：2009-01-08
申请人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
发明人： Mohamed Hassan Abu-Rahma , Seung-Chul Song , Sei Seung Yoon , Dongkyu Park , Cheng Zhong , Anosh B. Davierwalla
IPC分类号： G11C11/02 , G11C11/14 , G11C11/416
CPC分类号： G11C11/1675 , G11C11/1657 , G11C11/1659 , G11C11/1673
摘要： A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.
摘要翻译：公开了一种在磁随机存取存储器中读取和写入数据的系统和方法。在特定实施例中，器件包括自旋转移转矩磁隧道结（STT-MTJ）元件和具有耦合到STT-MTJ元件的第一栅极和第二栅极的晶体管。

3. 发明申请

US20100061144A1 Memory Device for Resistance-Based Memory Applications 有权
标题翻译：用于基于电阻的存储器应用的存储器件
公开(公告)号：US20100061144A1
公开(公告)日：2010-03-11
申请号：US12206933
申请日：2008-09-09
申请人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
发明人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/1673
摘要： In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.
摘要翻译：在特定实施例中，公开了一种存储器件，其包括存储单元，该存储单元包括耦合到存取晶体管的基于电阻的存储元件。存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。存储器件还包括第一放大器，其被配置为将存储器单元耦合到大于电压限制的电源电压，以基于通过存储器单元的电流来产生数据信号。第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管。钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

4. 发明授权

US08228714B2 Memory device for resistance-based memory applications 有权
标题翻译：用于基于电阻的存储器应用的存储器件
公开(公告)号：US08228714B2
公开(公告)日：2012-07-24
申请号：US12206933
申请日：2008-09-09
申请人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
发明人： Anosh B. Davierwalla , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma , Mehdi Hamidi Sani , Sei Seung Yoon
IPC分类号： G11C11/00
CPC分类号： G11C11/1673
摘要： In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.
摘要翻译：在特定实施例中，公开了一种存储器件，其包括存储单元，该存储单元包括耦合到存取晶体管的基于电阻的存储元件。存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。存储器件还包括第一放大器，其被配置为将存储器单元耦合到大于电压限制的电源电压，以基于通过存储器单元的电流来产生数据信号。第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管。钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

5. 发明授权

US07672175B2 System and method of selectively applying negative voltage to wordlines during memory device read operation 有权
标题翻译：在存储器件读取操作期间选择性地向字线施加负电压的系统和方法
公开(公告)号：US07672175B2
公开(公告)日：2010-03-02
申请号：US11972696
申请日：2008-01-11
申请人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma
发明人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma
IPC分类号： G11C7/22
CPC分类号： G11C8/08 , G11C11/1673
摘要： Systems and methods of selectively applying negative voltage to word lines during memory device read operation are disclosed. In an embodiment, a memory device includes a word line logic circuit coupled to a plurality of word lines and adapted to selectively apply a positive voltage to a selected word line coupled to a selected memory cell that includes a magnetic tunnel junction (MTJ) device and to apply a negative voltage to unselected word lines.
摘要翻译：公开了在存储器件读取操作期间选择性地向字线施加负电压的系统和方法。在一个实施例中，存储器件包括字线逻辑电路，其耦合到多个字线并且适于选择性地将正电压施加到与包括磁性隧道结（MTJ）器件的选定存储器单元耦合的所选择的字线，对未选择的字线施加负电压。

6. 发明申请

US20090180315A1 System and Method of Selectively Applying Negative Voltage to Wordlines During Memory Device Read Operation 有权
标题翻译：在存储器读取操作期间选择性地对字线施加负电压的系统和方法
公开(公告)号：US20090180315A1
公开(公告)日：2009-07-16
申请号：US11972696
申请日：2008-01-11
申请人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma
发明人： Sei Seung Yoon , Cheng Zhong , Dongkyu Park , Mohamed Hassan Abu-Rahma
IPC分类号： G11C11/14
CPC分类号： G11C8/08 , G11C11/1673
摘要： Systems and methods of selectively applying negative voltage to word lines during memory device read operation are disclosed. In an embodiment, a memory device includes a word line logic circuit coupled to a plurality of word lines and adapted to selectively apply a positive voltage to a selected word line coupled to a selected memory cell that includes a magnetic tunnel junction (MTJ) device and to apply a negative voltage to unselected word lines.
摘要翻译：公开了在存储器件读取操作期间选择性地向字线施加负电压的系统和方法。在一个实施例中，存储器件包括字线逻辑电路，其耦合到多个字线并且适于选择性地将正电压施加到与包括磁性隧道结（MTJ）器件的所选存储器单元耦合的所选择的字线，对未选择的字线施加负电压。

7. 发明申请

US20100188894A1 IN-SITU RESISTANCE MEASUREMENT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) 有权
标题翻译：磁性随机存取存储器（MRAM）的现场电阻测量
公开(公告)号：US20100188894A1
公开(公告)日：2010-07-29
申请号：US12361588
申请日：2009-01-29
申请人： Hari Rao , Sei Seung Yoon , Xiaochun Zhu , Mohamed Hassan Abu-Rahma
发明人： Hari Rao , Sei Seung Yoon , Xiaochun Zhu , Mohamed Hassan Abu-Rahma
IPC分类号： G11C11/14 , G01R27/08 , G11C8/00
CPC分类号： G11C11/1653 , G11C7/14 , G11C11/1655 , G11C11/1673
摘要： A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined. A variable voltage is applied to a replica cell not having an MTJ and comprising a replica cell transistor in a conducting state. A value of the variable voltage is determined, wherein a resulting current through the replica cell is substantially the same as the current through the memory cell. The MTJ resistance is computed by taking the difference of the memory cell voltage and the determined variable replica cell voltage and dividing the result by the determined memory cell current.
摘要翻译：一种测量MRAM存储单元的磁性隧道结（MTJ）的电阻的方法包括将一个所选电平的电压施加到一个与导通状态的存储单元晶体管串联的MTJ的存储单元。确定通过存储单元的电流。可变电压被施加到不具有MTJ并且包括处于导通状态的复制单元晶体管的复制单元。确定可变电压的值，其中通过复制单元的结果电流与通过存储单元的电流基本相同。通过取存储单元电压和确定的可变副本单元电压的差值并将结果除以所确定的存储单元电流来计算MTJ电阻。

8. 发明申请

US20090158101A1 Adapting Word Line Pulse Widths in Memory Systems 有权
标题翻译：适应内存系统中的字线脉冲宽度
公开(公告)号：US20090158101A1
公开(公告)日：2009-06-18
申请号：US12328156
申请日：2008-12-04
申请人： Mohamed Hassan Abu-Rahma , Sei Seung Yoon
发明人： Mohamed Hassan Abu-Rahma , Sei Seung Yoon
IPC分类号： G11C29/12 , G06F11/00
CPC分类号： G11C29/50 , G11C7/22 , G11C8/08 , G11C29/028 , G11C29/50012 , G11C2029/0407 , G11C2029/1202
摘要： Systems, circuits and methods for adapting word line (WL) pulse widths used in memory systems are disclosed. One embodiment of the invention is directed to an apparatus comprising a memory system. The memory system comprises: a memory operating according to a wordline (WL) pulse with an associated WL pulse width; a built-in self-test (BIST) unit that interfaces with the memory, the BIST unit being configured to run a self-test of the internal functionality of the memory and provide a signal indicating if the memory passed or failed the self-test; and an adaptive WL control circuit that interfaces with the BIST unit and the memory, the adaptive WL control circuit being configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit.
摘要翻译：公开了用于适应存储器系统中使用的字线（WL）脉冲宽度的系统，电路和方法。本发明的一个实施例涉及一种包括存储器系统的装置。存储器系统包括：根据具有相关联的WL脉冲宽度的字线（WL）脉冲操作的存储器; 与内存接口的内置自检（BIST）单元，BIST单元被配置为对存储器的内部功能进行自检，并提供一个信号，指示存储器是否通过或失败自检 ; 以及与所述BIST单元和所述存储器接口的自适应WL控制电路，所述自适应WL控制电路被配置为基于由所述BIST单元提供的信号来调整所述存储器的WL脉冲宽度。

9. 发明授权

US07882407B2 Adapting word line pulse widths in memory systems 有权
标题翻译：适应内存系统中的字线宽度
公开(公告)号：US07882407B2
公开(公告)日：2011-02-01
申请号：US12328156
申请日：2008-12-04
申请人： Mohamed Hassan Abu-Rahma , Sei Seung Yoon
发明人： Mohamed Hassan Abu-Rahma , Sei Seung Yoon
IPC分类号： G11C29/00 , G01R31/30
CPC分类号： G11C29/50 , G11C7/22 , G11C8/08 , G11C29/028 , G11C29/50012 , G11C2029/0407 , G11C2029/1202
摘要： A memory system and method using adaptive word line (WL) pulse widths, including a memory operating according to a wordline (WL) pulse with an associated WL pulse width, and a built-in self-test (BIST) unit that interfaces with the memory, the BIST unit being configured to run a self-test of the internal functionality of the memory and provide a signal indicating if the memory passed or failed the self-test. An adaptive WL control circuit that interfaces with the BIST unit and the memory, the adaptive WL control circuit being configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit.
摘要翻译：一种使用自适应字线（WL）脉冲宽度的存储器系统和方法，包括根据具有相关联的WL脉冲宽度的字线（WL）脉冲操作的存储器，以及内置自检（BIST）单元，其与存储器，BIST单元被配置为运行对存储器的内部功能的自检，并提供指示存储器是否通过或失败的自检的信号。一种与BIST单元和存储器接口的自适应WL控制电路，该自适应WL控制电路被配置为基于由BIST单元提供的信号来调整存储器的WL脉冲宽度。

10. 发明授权

US07829951B2 Method of fabricating a fin field effect transistor (FinFET) device 有权
标题翻译：制造鳍式场效应晶体管（FinFET）器件的方法
公开(公告)号：US07829951B2
公开(公告)日：2010-11-09
申请号：US12266183
申请日：2008-11-06
申请人： Seung-Chul Song , Mohamed Hassan Abu-Rahma , Beom-Mo Han
发明人： Seung-Chul Song , Mohamed Hassan Abu-Rahma , Beom-Mo Han
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.
摘要翻译：公开了一种使用鳍状场效应晶体管（FINFET）制造半导体的方法。在特定实施例中，一种方法包括在硅衬底上沉积第一虚设结构，该第一虚设结构具有由第一宽度分隔的第一侧壁和第二侧壁。该方法还包括在沉积第一虚拟结构的同时在硅衬底上沉积第二虚拟结构。第二虚拟结构具有分隔第二宽度的第三侧壁和第四侧壁。第二宽度基本上大于第一宽度。第一虚拟结构用于形成以大约第一宽度分开的第一对散热片。第二虚拟结构用于形成分开大约第二宽度的第二对散热片。

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