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1. 发明申请

US20130146763A1 Image Processing Device, Charged Particle Beam Device, Charged Particle Beam Device Adjustment Sample, and Manufacturing Method Thereof 有权
标题翻译：图像处理装置，带电粒子束装置，带电粒子束装置调整样品及其制造方法
公开(公告)号：US20130146763A1
公开(公告)日：2013-06-13
申请号：US13700096
申请日：2011-05-25
申请人： Hiroki Kawada , Osamu Inoue , Miyako Matsui , Takahiro Kawasaki , Naoshi Itabashi , Takashi Takahama , Katsumi Setoguchi , Osamu Komuro
发明人： Hiroki Kawada , Osamu Inoue , Miyako Matsui , Takahiro Kawasaki , Naoshi Itabashi , Takashi Takahama , Katsumi Setoguchi , Osamu Komuro
IPC分类号： G01B15/00 , G06K9/62
CPC分类号： G01B15/00 , G06K9/6201 , H01J37/222 , H01J37/28 , H01J2237/24578 , H01J2237/2817 , H01J2237/2826 , Y10T428/24355
摘要： An object of the present invention is to provide an image processing apparatus that quickly and precisely measures or evaluates a distortion in a field of view and a charged particle beam apparatus. To attain the object, an image processing apparatus or the like is proposed which acquires a first image of a first area of an imaging target and a second image of a second area that is located at a different position than the first area and partially overlaps with the first area and determines the distance between a measurement point in the second image and a second part of the second image that corresponds to a particular area for a plurality of sites in the overlapping area of the first image and the second image.
摘要翻译：本发明的目的是提供一种快速且精确地测量或评估视野中的失真和带电粒子束装置的图像处理装置。为了实现该目的，提出了一种图像处理装置等，其获取成像目标的第一区域的第一图像和位于与第一区域不同的位置的第二区域的第二图像，并且部分地与所述第一区域确定所述第二图像中的测量点和所述第二图像的与所述第一图像和所述第二图像的重叠区域中的多个位置的特定区域相对应的第二部分之间的距离。

2. 发明授权

US06700122B2 Wafer inspection system and wafer inspection process using charged particle beam 失效
标题翻译：晶圆检查系统和使用带电粒子束的晶圆检查过程
公开(公告)号：US06700122B2
公开(公告)日：2004-03-02
申请号：US10035150
申请日：2002-01-04
申请人： Miyako Matsui , Mari Nozoe , Atsuko Takafuji
发明人： Miyako Matsui , Mari Nozoe , Atsuko Takafuji
IPC分类号： G01R3126
CPC分类号： H01J37/28 , H01J2237/281 , H01J2237/2817
摘要： The present invention provides a wafer inspection technique capable of detecting a defect in a wafer on which a pattern having a large step such as a contact hole being subjected to a semiconductor manufacturing process is formed and obtaining information such as the position and kind of a defect such as a hole with open contact failure caused in dry etching process at high speed. A wafer on which a pattern having a large step being subjected to a semiconductor manufacturing process is formed is scanned and irradiated with an electron beam having irradiation energy which is in a range from 100 eV to 1,000 eV, and a defect is detected at high speed from an image of secondary electrons generated. Before the secondary electron image is captured, the wafer is irradiated with an electron beam at high speed while being moved to thereby charge the surface of the wafer with a desired charging voltage. The kind of the defect is determined from the captured secondary electron image, and a distribution of defects in the plane of the wafer is displayed.
摘要翻译：本发明提供一种晶片检查技术，其能够检测在其上形成具有大台阶的图案的晶片中的缺陷，所述图案具有形成半导体制造工艺的接触孔，诸如缺陷的位置和种类等信息例如在高速干燥蚀刻工艺中引起的具有开放接触故障的孔。对其上形成具有大步骤的图案进行半导体制造处理的晶片被扫描并照射具有在100eV至1,000eV范围内的照射能量的电子束，并且以高速检测缺陷从二次电子的图像生成。在捕获二次电子图像之前，在移动的同时以高速度用电子束照射晶片，从而以期望的充电电压对晶片的表面充电。从捕获的二次电子图像确定缺陷的种类，并且显示晶片的平面中的缺陷的分布。

3. 发明授权

US06753524B2 Inspection system and inspection process for wafer with circuit using charged-particle beam 失效
标题翻译：使用带电粒子束的电路晶圆的检查系统和检查过程
公开(公告)号：US06753524B2
公开(公告)日：2004-06-22
申请号：US10166774
申请日：2002-06-12
申请人： Miyako Matsui , Mari Nozoe
发明人： Miyako Matsui , Mari Nozoe
IPC分类号： G01B1100
CPC分类号： H01J37/28 , H01J2237/0047 , H01J2237/2817
摘要： In a method for inspecting positions and types of defects on wafers with circuit patterns in a semiconductor manufacturing process, inspection is made regardless of the types and materials of junctions of circuit patterns of the semiconductor devices, different kinds of defects being distinguished from one another. Further, electrification of the circuit pattern is prevented, and the area to be exposed to an electron beam is controlled evenly and at a desired voltage. During inspection of the positions and types of defects on a wafer using a charged-particle beam from a charged-particle source, an optical beam from an optical source as well as a charged-particle beam are applied to a junction of the circuit pattern of the wafer placed on a wafer holder. Thus, regardless of the types and materials of circuit patterns, a highly sensitive inspection is made according to contrasts in the defects of a captured image.
摘要翻译：在半导体制造过程中用电路图案检查晶片上的缺陷的位置和类型的方法中，无论半导体器件的电路图案的结的类型和材料如何，都进行检查，不同种类的缺陷彼此区分。此外，防止电路图案的通电，并且暴露于电子束的区域被均匀地控制并且处于期望的电压。在使用来自带电粒子源的带电粒子束来检查晶片上的缺陷的位置和类型时，来自光源的光束以及带电粒子束被施加到电荷模式将晶片放置在晶片保持器上。因此，无论电路图案的类型和材料如何，根据捕获图像的缺陷的对比度进行高度敏感的检查。

4. 发明授权

US07368713B2 Method and apparatus for inspecting semiconductor device 有权
标题翻译：用于检查半导体器件的方法和装置
公开(公告)号：US07368713B2
公开(公告)日：2008-05-06
申请号：US11189898
申请日：2005-07-27
申请人： Miyako Matsui
发明人： Miyako Matsui
IPC分类号： G21K7/00 , G01N23/203 , G01N23/225 , H01J37/28
CPC分类号： H01J37/28 , G01N2223/07 , G01N2223/414 , G01N2223/6116 , H01J2237/24578 , H01J2237/2611
摘要： A method and apparatus for inspecting a wafer during a semiconductor device fabrication process. The apparatus performs, only via observation from the wafer's top surface, inspection and quantitative evaluation of a portion that is in the shadow of an incident electron beam and a buried structure in the wafer. To this end, the electron beam is emitted so that it partially penetrates a wafer surface and reaches an unexposed pattern portion to the beam. When a stereoscopic structure is constructed from the scan image based on a secondarily generated signal, generate a stereoscopic model of a pattern being tested. The secondary signal is used to detect position information of a pattern edge(s) and signal intensity. Then, use the information to calculate more than one feature quantity of the test pattern. From the calculated feature quantities, the stereoscopic structure is constructed for displaying a 3D structure of the pattern.
摘要翻译：一种用于在半导体器件制造工艺期间检查晶片的方法和装置。该装置仅通过从晶片顶表面的观察来执行在晶片中的入射电子束和掩埋结构的阴影中的部分的检查和定量评估。为此，发射电子束，使其部分地穿透晶片表面并到达未曝光的图案部分。当基于二次生成的信号从扫描图像构建立体结构时，生成被测试图案的立体模型。辅助信号用于检测图案边缘和信号强度的位置信息。然后，使用该信息来计算测试图案的多个特征量。根据计算出的特征量，构造用于显示图案的3D结构的立体结构。

5. 发明授权

US09702695B2 Image processing device, charged particle beam device, charged particle beam device adjustment sample, and manufacturing method thereof 有权
公开(公告)号：US09702695B2
公开(公告)日：2017-07-11
申请号：US13700096
申请日：2011-05-25
申请人： Hiroki Kawada , Osamu Inoue , Miyako Matsui , Takahiro Kawasaki , Naoshi Itabashi , Takashi Takahama , Katsumi Setoguchi , Osamu Komuro
发明人： Hiroki Kawada , Osamu Inoue , Miyako Matsui , Takahiro Kawasaki , Naoshi Itabashi , Takashi Takahama , Katsumi Setoguchi , Osamu Komuro
IPC分类号： G01N23/00 , G01B15/00 , H01J37/22 , H01J37/28 , G06K9/62
CPC分类号： G01B15/00 , G06K9/6201 , H01J37/222 , H01J37/28 , H01J2237/24578 , H01J2237/2817 , H01J2237/2826 , Y10T428/24355
摘要： An object of the present invention is to provide an image processing apparatus that quickly and precisely measures or evaluates a distortion in a field of view and a charged particle beam apparatus. To attain the object, an image processing apparatus or the like is proposed which acquires a first image of a first area of an imaging target and a second image of a second area that is located at a different position than the first area and partially overlaps with the first area and determines the distance between a measurement point in the second image and a second part of the second image that corresponds to a particular area for a plurality of sites in the overlapping area of the first image and the second image.

6. 发明申请

US20060043292A1 Method and apparatus for inspecting semiconductor device 有权
标题翻译：用于检查半导体器件的方法和装置
公开(公告)号：US20060043292A1
公开(公告)日：2006-03-02
申请号：US11189898
申请日：2005-07-27
申请人： Miyako Matsui
发明人： Miyako Matsui
IPC分类号： G21K7/00
CPC分类号： H01J37/28 , G01N2223/07 , G01N2223/414 , G01N2223/6116 , H01J2237/24578 , H01J2237/2611
摘要： A method and apparatus for inspecting a wafer during a semiconductor device fabrication process. The apparatus performs, only via observation from the wafer's top surface, inspection and quantitative evaluation of a portion that is in the shadow of an incident electron beam and a buried structure in the wafer. To this end, the electron beam is emitted so that it partially penetrates a wafer surface and reaches an unexposed pattern portion to the beam. When a stereoscopic structure is constructed from the scan image based on a secondarily generated signal, generate a stereoscopic model of a pattern being tested. The secondary signal is used to detect position information of a pattern edge(s) and signal intensity. Then, use the information to calculate more than one feature quantity of the test pattern. From the calculated feature quantities, the stereoscopic structure is constructed for displaying a 3D structure of the pattern.
摘要翻译：一种用于在半导体器件制造工艺期间检查晶片的方法和装置。该装置仅通过从晶片顶表面的观察来执行在晶片中的入射电子束和掩埋结构的阴影部分的检查和定量评估。为此，发射电子束，使其部分地穿透晶片表面并到达未曝光的图案部分。当基于二次生成的信号从扫描图像构建立体结构时，生成被测试图案的立体模型。辅助信号用于检测图案边缘和信号强度的位置信息。然后，使用该信息来计算测试图案的多个特征量。根据计算出的特征量，构造用于显示图案的3D结构的立体结构。

7. 发明授权

US5981399A Method and apparatus for fabricating semiconductor devices 失效
标题翻译：用于制造半导体器件的方法和装置
公开(公告)号：US5981399A
公开(公告)日：1999-11-09
申请号：US894308
申请日：1997-08-14
申请人： Yoshio Kawamura , Tatuharu Yamamoto , Shigeo Moriyama , Yoshifumi Kawamoto , Natsuki Yokoyama , Fumihiko Uchida , Minoru Hidaka , Miyako Matsui
发明人： Yoshio Kawamura , Tatuharu Yamamoto , Shigeo Moriyama , Yoshifumi Kawamoto , Natsuki Yokoyama , Fumihiko Uchida , Minoru Hidaka , Miyako Matsui
IPC分类号： B65G49/07 , H01L21/00 , H01L21/677
CPC分类号： H01L21/67167 , H01L21/67196 , H01L21/67742 , H01L21/67748
摘要： A semiconductor device fabrication apparatus having multiple processing chambers for different processes, where a substrate is carried in and out in a sophisticated manner, with their different internal ambient conditions being retained, so that the substrate is free from contamination, thereby manufacturing high-quality semiconductor devices at high throughput. The apparatus includes a movable buffer chamber having a wafer carriage means within a transfer chamber which faces a process chamber, an evacuation means which evacuates of gas the buffer chamber, transfer chamber and process chamber independently, a gas feed means, and a control means.
摘要翻译： PCT No.PCT / JP95 / 00210 Sec。 371日期1997年8月14日 102（e）日期1997年8月14日PCT提交1995年2月15日PCT公布。公开号WO96 / 25760 PCT 日期1996年8月22日一种半导体器件制造装置，具有用于不同工艺的多个处理室，其中衬底以复杂的方式进出，同时保持其不同的内部环境条件，使得衬底没有污染，从而以高产量制造高品质半导体器件。该装置包括可移动缓冲室，其具有面向处理室的传送室内的晶片托架装置，独立地排出缓冲室，传送室和处理室的气体的抽气装置，气体供给装置和控制装置。

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