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1. 发明申请

US20100329026A1 SEMICONDUCTOR MEMORY DEVICE WITH CHARGE ACCUMULATION LAYER 审中-公开
标题翻译：具有充电累积层的半导体存储器件
公开(公告)号：US20100329026A1
公开(公告)日：2010-12-30
申请号：US12822703
申请日：2010-06-24
申请人： Mitsutoshi NAKAMURA , Takeshi Shimane , Michiru Hogyoku , Katsuaki Isobe , Naoyuki Shigyo
发明人： Mitsutoshi NAKAMURA , Takeshi Shimane , Michiru Hogyoku , Katsuaki Isobe , Naoyuki Shigyo
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元，第一和第二选择晶体管，源极线，温度监视器和源极线电压控制器。存储单元串联连接在第一选择晶体管的源极和第二选择晶体管的漏极之间。温度监视器监视半导体衬底的温度。源极线电压控制器在读取操作中以源极线和半导体衬底之间的电位差随着由温度监视器监测的温度的升高而增加的电压施加电压，在第二选择晶体管的源极和半导体衬底之间施加反向偏压。

2. 发明授权

US08503245B2 Non-volatile semiconductor memory device and a programming method thereof 有权
标题翻译：非易失性半导体存储器件及其编程方法
公开(公告)号：US08503245B2
公开(公告)日：2013-08-06
申请号：US13041041
申请日：2011-03-04
申请人： Kunihiro Yamada , Naoyuki Shigyo , Michiru Hogyoku , Hideto Horii
发明人： Kunihiro Yamada , Naoyuki Shigyo , Michiru Hogyoku , Hideto Horii
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor. Thereafter, the programming means applies an intermediate voltage incremented stepwise from the initial intermediate voltage, to one of the respective memory cells adjacent to the programming target memory cell transistor, while applying a constant final programming voltage to the programming target memory cell transistor.
摘要翻译：根据本发明的实施例的一个方面的非易失性半导体存储器件包括：半导体衬底; 元素区域多个存储单元晶体管，其各自包括控制栅电极; 以及通过向编程目标存储单元晶体管施加编程电压将数据编程到编程目标存储单元晶体管的编程装置。此外，编程装置将从初始编程电压逐步增加的编程电压施加到编程目标存储单元晶体管，同时向与编程目标存储单元晶体管相邻的存储单元晶体管施加恒定的初始中间电压。此后，编程装置将从初始中间电压逐步增加的中间电压施加到与编程目标存储单元晶体管相邻的各个存储单元之一，同时向编程目标存储单元晶体管施加恒定的最终编程电压。

3. 发明申请

US20110228610A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A PROGRAMMING METHOD THEREOF 有权
标题翻译：非挥发性半导体存储器件及其编程方法
公开(公告)号：US20110228610A1
公开(公告)日：2011-09-22
申请号：US13041041
申请日：2011-03-04
申请人： Kunihiro Yamada , Naoyuki Shigyo , Michiru Hogyoku , Hideto Horii
发明人： Kunihiro Yamada , Naoyuki Shigyo , Michiru Hogyoku , Hideto Horii
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor. Thereafter, the programming means applies an intermediate voltage incremented stepwise from the initial intermediate voltage, to one of the respective memory cells adjacent to the programming target memory cell transistor, while applying a constant final programming voltage to the programming target memory cell transistor.
摘要翻译：根据本发明的实施例的一个方面的非易失性半导体存储器件包括：半导体衬底; 元素区域多个存储单元晶体管，其各自包括控制栅电极; 以及通过向编程目标存储单元晶体管施加编程电压将数据编程到编程目标存储单元晶体管的编程装置。此外，编程装置将从初始编程电压逐步增加的编程电压施加到编程目标存储单元晶体管，同时向与编程目标存储单元晶体管相邻的存储单元晶体管施加恒定的初始中间电压。此后，编程装置将从初始中间电压逐步增加的中间电压施加到与编程目标存储单元晶体管相邻的各个存储单元之一，同时向编程目标存储单元晶体管施加恒定的最终编程电压。

4. 发明授权

US08369152B2 Semiconductor memory device including charge accumulation layer 有权
标题翻译：半导体存储器件包括电荷累积层
公开(公告)号：US08369152B2
公开(公告)日：2013-02-05
申请号：US12817665
申请日：2010-06-17
申请人： Takeshi Shimane , Naoyuki Shigyo , Mutsuo Morikado
发明人： Takeshi Shimane , Naoyuki Shigyo , Mutsuo Morikado
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： H01L27/11568 , G11C16/0483 , G11C16/10
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.
摘要翻译：根据一个实施例，半导体存储器件包括半导体衬底，没有源极区和漏极区的存储单元和第一绝缘膜。存储单元在半导体衬底上彼此相邻地布置，并且包括包括电荷累积层的第一栅电极。当向未选择的存储单元之一的第一栅电极施加电压时，在半导体衬底中形成用作所选存储单元的源极区或漏极区的电流路径。第一绝缘膜形成在半导体衬底上以填充彼此相邻的存储单元的第一栅电极之间的区域。

5. 发明申请

US20100322009A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING CHARGE ACCUMULATION LAYER 有权
标题翻译：半导体存储器件，包括充电累积层
公开(公告)号：US20100322009A1
公开(公告)日：2010-12-23
申请号：US12817665
申请日：2010-06-17
申请人： Takeshi SHIMANE , Naoyuki Shigyo , Mutsuo Morikado
发明人： Takeshi SHIMANE , Naoyuki Shigyo , Mutsuo Morikado
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0483 , G11C16/10
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.
摘要翻译：根据一个实施例，半导体存储器件包括半导体衬底，没有源极区和漏极区的存储单元和第一绝缘膜。存储单元在半导体衬底上彼此相邻地布置，并且包括包括电荷累积层的第一栅电极。当向未选择的存储单元之一的第一栅电极施加电压时，在半导体衬底中形成用作所选存储单元的源极区或漏极区的电流路径。第一绝缘膜形成在半导体衬底上以填充彼此相邻的存储单元的第一栅电极之间的区域。

6. 发明授权

US07999324B2 Semiconductor device including overcurrent protection element 失效
标题翻译：半导体装置包括过电流保护元件
公开(公告)号：US07999324B2
公开(公告)日：2011-08-16
申请号：US11291436
申请日：2005-11-30
申请人： Naoyuki Shigyo , Kentaro Watanabe
发明人： Naoyuki Shigyo , Kentaro Watanabe
IPC分类号： H01L23/62 , H01L29/76
CPC分类号： H01L29/665 , H01L27/0266 , H01L29/0653 , H01L29/41758 , H01L29/4238 , H01L29/7833 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fourth semiconductor region is formed in the semiconductor substrate between the second semiconductor region and the third semiconductor region and has an electric resistance higher than the first, second, and third semiconductor regions. In a direction perpendicular to a direction to connect the first and second semiconductor regions, the fourth semiconductor region has a width smaller than that of the semiconductor substrate sandwiched between the first semiconductor region and the second semiconductor region. The gate electrode is formed above the semiconductor substrate between the first semiconductor region and the second semiconductor region. The silicide layer is formed on each of the first, second, third semiconductor regions and the gate electrode.
摘要翻译：半导体器件包括第一，第二，第三和第四半导体区域，栅电极和硅化物层。第一，第二和第三半导体区域形成在半导体衬底中，同时彼此间隔开。第四半导体区域形成在第二半导体区域和第三半导体区域之间的半导体衬底中，并且具有高于第一，第二和第三半导体区域的电阻。在垂直于连接第一和第二半导体区域的方向的方向上，第四半导体区域的宽度小于夹在第一半导体区域和第二半导体区域之间的半导体衬底的宽度。栅极电极形成在第一半导体区域和第二半导体区域之间的半导体衬底之上。硅化物层形成在第一，第二，第三半导体区域和栅电极中的每一个上。

7. 发明授权

US07373627B2 Method of designing wiring structure of semiconductor device and wiring structure designed accordingly 失效
公开(公告)号：US07373627B2
公开(公告)日：2008-05-13
申请号：US11244294
申请日：2005-10-06
申请人： Naoyuki Shigyo , Tetsuya Yamaguchi
发明人： Naoyuki Shigyo , Tetsuya Yamaguchi
IPC分类号： G06F17/50
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δP) for the wiring structure, a tolerance (ξC) for the capacitance variation ratio (ΔC/C), and a tolerance (ξRC) for the resistance-by-capacitance variation ratio (Δ(RC)/(RC)), evaluates a fringe capacitance ratio (F=CF/CP) according to a fringe capacitance CF and parallel-plate capacitance CP of the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the following: For ⁢  ΔC C  ≤ ξ ⁢ C , ⁢ F ≥ δ P ξ C - 1 ( 1 ) For ⁢  Δ ⁡ ( RC ) RC  ≤ ξ RC , ⁢ F ≤ ( 1 - δ P ) ⁢ δ P δ P - ξ RC - 1 ( 2 ) The method employs an equivalent-variations condition defined as |ΔC/C|=|Δ(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure.

8. 发明授权

US06222224B1 Erasable and programmable nonvolatile semiconductor memory, semiconductor integrated circuit device having the semiconductor memory and method of manufacturing the semiconductor memory 失效
标题翻译：可擦除和可编程的非易失性半导体存储器，具有半导体存储器的半导体集成电路器件和半导体存储器的制造方法
公开(公告)号：US06222224B1
公开(公告)日：2001-04-24
申请号：US08994482
申请日：1997-12-19
申请人： Naoyuki Shigyo
发明人： Naoyuki Shigyo
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/0483 , H01L27/115 , H01L29/7883
摘要： A nonvolatile semiconductor memory has memory cells (1) each having an insulated-gate FET that has an information storage part. A semiconductor region (27) is formed at the surface of a channel region of each memory cell. The semiconductor region has the same conductivity type as a channel conductivity type and functions to decrease the strength of an electric field at the surface of the channel region. If the insulated-gate FET is of an n-channel type, the semiconductor region is of an n-type. The semiconductor region suppresses threshold voltage variations among the insulated-gate FETs of the memory cells and prevents soft-writing in the memory cells.
摘要翻译：非易失性半导体存储器具有各自具有具有信息存储部分的绝缘栅FET的存储单元（1）。半导体区域（27）形成在每个存储单元的沟道区域的表面。半导体区域具有与沟道导电型相同的导电类型，并且具有降低沟道区表面的电场强度的作用。如果绝缘栅FET为n沟道型，则半导体区域为n型。半导体区域抑制存储单元的绝缘栅FET之间的阈值电压变化，并防止存储单元中的软写入。

9. 发明授权

US6051452A Method for manufacturing a semiconductor device with ion implantation 失效
标题翻译：用于制造具有离子注入的半导体器件的方法
公开(公告)号：US6051452A
公开(公告)日：2000-04-18
申请号：US3339
申请日：1998-01-06
申请人： Naoyuki Shigyo , Toshiyuki Enda
发明人： Naoyuki Shigyo , Toshiyuki Enda
IPC分类号： H01L21/336 , H01L21/84 , H01L29/786 , H01L31/0392 , H01L31/113
CPC分类号： H01L29/66772 , H01L21/84 , H01L29/78603 , H01L29/78606
摘要： A silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A silicon oxide layer serving as an insulation layer is formed on the channel region. A gate terminal is formed on the silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.
摘要翻译：在p型半导体衬底上形成用作绝缘层的氧化硅层。在p型衬底110上形成n +型源极和漏极区，其间具有间隔。沟道区域介于源区和漏区之间。在沟道区上形成用作绝缘层的氧化硅层。在氧化硅层上形成栅极端子。在源极和漏极区域的p型半导体衬底中分别形成高浓度p型区域。

10. 发明授权

US4941114A Triangular mesh generation method 失效
标题翻译：三角网格生成方法
公开(公告)号：US4941114A
公开(公告)日：1990-07-10
申请号：US169480
申请日：1988-03-17
申请人： Naoyuki Shigyo , Koichi Sato
发明人： Naoyuki Shigyo , Koichi Sato
IPC分类号： G06F17/11 , G06T17/20
CPC分类号： G06T17/20
摘要： A triangular mesh generation apparatus has a feedback rate calculation unit and a triangular mesh generation unit. The feedback rate calculation unit obtains feedback rate r.sub.i for a given node i from the following relationship: ##EQU1## where d.sub.i is a distance between the respective adjacent nodes, a is a distance between nodes i-1 and i, b is a distance between nodes i and i+1, and .alpha.>0. The triangular ratio generation unit generates triangular meshes as follows:(1) When .theta..ltoreq.90.degree., a triangular element is generated by node i and its adjacent nodes i-1 and i+1.(2) When 90.degree.
摘要翻译：三角形网格生成装置具有反馈率计算单元和三角形网格生成单元。反馈率计算单元从以下关系获得给定节点i的反馈速率ri：其中di是各个相邻节点之间的距离，a是节点i-1和i之间的距离，b是节点i-1和i之间的距离，节点i和i + 1，alpha> 0。三角形比例生成单元生成三角形网格如下：（1）当θ= 90°时，由节点i及其相邻节点i-1和i + 1生成三角形元素。（2）当90°<150°时，在从节点i的距离l1'= rix1处将内部边界角θ分割成两个等分的线上获得节点j1'。然后，分别由节点i，i-1和j1'以及节点i，i + 1和j1'生成两个三角形元素。（3）当150°<180°时，在距离l2'= rix2处将内部边界角θ分割成三个相等部分的一条线上获得节点j2'，并且节点j3'处于距离节点i的距离l3'= rix3的另一条线。然后，分别由节点i，i-1和j2'，i，j2'和j3'以及节点i，i + 1和j3'生成三个三角形元素。这里，l2 = 3 2ROOT axb2和l3 = 3 2ROOT axb2。

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