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1. 发明申请

US20100329026A1 SEMICONDUCTOR MEMORY DEVICE WITH CHARGE ACCUMULATION LAYER 审中-公开
标题翻译：具有充电累积层的半导体存储器件
公开(公告)号：US20100329026A1
公开(公告)日：2010-12-30
申请号：US12822703
申请日：2010-06-24
申请人： Mitsutoshi NAKAMURA , Takeshi Shimane , Michiru Hogyoku , Katsuaki Isobe , Naoyuki Shigyo
发明人： Mitsutoshi NAKAMURA , Takeshi Shimane , Michiru Hogyoku , Katsuaki Isobe , Naoyuki Shigyo
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元，第一和第二选择晶体管，源极线，温度监视器和源极线电压控制器。存储单元串联连接在第一选择晶体管的源极和第二选择晶体管的漏极之间。温度监视器监视半导体衬底的温度。源极线电压控制器在读取操作中以源极线和半导体衬底之间的电位差随着由温度监视器监测的温度的升高而增加的电压施加电压，在第二选择晶体管的源极和半导体衬底之间施加反向偏压。

2. 发明授权

US08503245B2 Non-volatile semiconductor memory device and a programming method thereof 有权
标题翻译：非易失性半导体存储器件及其编程方法
公开(公告)号：US08503245B2
公开(公告)日：2013-08-06
申请号：US13041041
申请日：2011-03-04
申请人： Kunihiro Yamada , Naoyuki Shigyo , Michiru Hogyoku , Hideto Horii
发明人： Kunihiro Yamada , Naoyuki Shigyo , Michiru Hogyoku , Hideto Horii
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor. Thereafter, the programming means applies an intermediate voltage incremented stepwise from the initial intermediate voltage, to one of the respective memory cells adjacent to the programming target memory cell transistor, while applying a constant final programming voltage to the programming target memory cell transistor.
摘要翻译：根据本发明的实施例的一个方面的非易失性半导体存储器件包括：半导体衬底; 元素区域多个存储单元晶体管，其各自包括控制栅电极; 以及通过向编程目标存储单元晶体管施加编程电压将数据编程到编程目标存储单元晶体管的编程装置。此外，编程装置将从初始编程电压逐步增加的编程电压施加到编程目标存储单元晶体管，同时向与编程目标存储单元晶体管相邻的存储单元晶体管施加恒定的初始中间电压。此后，编程装置将从初始中间电压逐步增加的中间电压施加到与编程目标存储单元晶体管相邻的各个存储单元之一，同时向编程目标存储单元晶体管施加恒定的最终编程电压。

3. 发明申请

US20110228610A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A PROGRAMMING METHOD THEREOF 有权
标题翻译：非挥发性半导体存储器件及其编程方法
公开(公告)号：US20110228610A1
公开(公告)日：2011-09-22
申请号：US13041041
申请日：2011-03-04
申请人： Kunihiro Yamada , Naoyuki Shigyo , Michiru Hogyoku , Hideto Horii
发明人： Kunihiro Yamada , Naoyuki Shigyo , Michiru Hogyoku , Hideto Horii
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor. Thereafter, the programming means applies an intermediate voltage incremented stepwise from the initial intermediate voltage, to one of the respective memory cells adjacent to the programming target memory cell transistor, while applying a constant final programming voltage to the programming target memory cell transistor.
摘要翻译：根据本发明的实施例的一个方面的非易失性半导体存储器件包括：半导体衬底; 元素区域多个存储单元晶体管，其各自包括控制栅电极; 以及通过向编程目标存储单元晶体管施加编程电压将数据编程到编程目标存储单元晶体管的编程装置。此外，编程装置将从初始编程电压逐步增加的编程电压施加到编程目标存储单元晶体管，同时向与编程目标存储单元晶体管相邻的存储单元晶体管施加恒定的初始中间电压。此后，编程装置将从初始中间电压逐步增加的中间电压施加到与编程目标存储单元晶体管相邻的各个存储单元之一，同时向编程目标存储单元晶体管施加恒定的最终编程电压。

4. 发明授权

US06835982B2 Semiconductor devices 失效
标题翻译：半导体器件
公开(公告)号：US06835982B2
公开(公告)日：2004-12-28
申请号：US10183888
申请日：2002-06-27
申请人： Michiru Hogyoku
发明人： Michiru Hogyoku
IPC分类号： H01L310392
CPC分类号： H01L29/66772 , H01L29/7841 , H01L29/78615
摘要： A SOI MOSFET 10 may be formed from silicon single crystal as a substrate body that is formed on an embedded oxide film 11. For example, a P-type body 12, a channel section 13, and N-type source region 14 and drain region 15 are formed therein. Low concentration N-type extension regions 18, a gate electrode 17 provided through a gate dielectric layer 16 and sidewalls 19 are formed therein. A body terminal 101 in which a resistance (body resistance) Rb between itself and a body is positively increased is provided, and the body terminal 101 is connected to a source region 14. This structure realizes a SOI MOSFET with a BTS (Body-Tied-to-Source) operation accompanied by a transient capacitive coupling of a body during a circuit operation.
摘要翻译：可以由形成在嵌入的氧化膜11上的基板的硅单晶形成SOI MOSFET 10.例如，P型体12，沟道部13，N型源极区14以及漏极区 15。低浓度N型延伸区域18，通过栅介质层16和侧壁19设置的栅电极17。提供了其本身和主体之间的电阻（体电阻）Rb正向增加的主体端子101，并且主体端子101连接到源极区域14.该结构实现了具有BTS（体线）的SOI MOSFET 到源）操作，伴随着在电路操作期间身体的瞬时电容耦合。

5. 发明授权

US06787851B2 Semiconductor devices including a silicon-on-insulator layer 失效
标题翻译：包括绝缘体上硅层的半导体器件
公开(公告)号：US06787851B2
公开(公告)日：2004-09-07
申请号：US10025347
申请日：2001-12-19
申请人： Michiru Hogyoku
发明人： Michiru Hogyoku
IPC分类号： H01L2701
CPC分类号： H01L29/78612 , H01L29/78654
摘要： A semiconductor device in accordance with one example of the present invention pertains to a semiconductor device to be used for a CMOS inverter circuit, comprising a BOX layer 2 formed on a silicon substrate 1, a SOI film 3 including single crystal Si formed on the BOX layer, a gate oxide film 4 formed on the SOI film 3, a gate electrode 5 formed on the gate oxide film, and diffusion layers 7, 8 for source/drain regions formed in source/drain regions of the SOI film 3, wherein, when a power supply voltage of 0.6 V is used, a thickness TSOI of the SOI film 3 is 0.084 &mgr;m or greater and 0.094 &mgr;m or smaller, and an impurity concentration of the SOI film is 7.95×1017/cm3 or greater and 8.05×1017/cm3 or smaller.
摘要翻译：根据本发明的一个示例的半导体器件涉及用于CMOS反相器电路的半导体器件，包括形成在硅衬底1上的BOX层2，包括形成在BOX上的单晶Si的SOI膜3 形成在SOI膜3上的栅极氧化膜4，形成在栅极氧化膜上的栅极电极5和形成在SOI膜3的源极/漏极区域中的源极/漏极区域的扩散层7,8，其中，当使用0.6V的电源电压时，SOI膜3的厚度TSOI为0.084μm以上且0.094μm以下，SOI膜的杂质浓度为7.95×10 17 / cm 3或更大和8.05×10 17 / cm 3或更小。

6. 发明授权

US07093214B2 Methods of extracting SPICE parameters, performing a spice calculation, and performing device simulation for a partially-depleted SOI MOSFET 失效
标题翻译：提取SPICE参数，执行香料计算以及对部分耗尽的SOI MOSFET执行器件仿真的方法
公开(公告)号：US07093214B2
公开(公告)日：2006-08-15
申请号：US10720740
申请日：2003-11-24
申请人： Michiru Hogyoku
发明人： Michiru Hogyoku
IPC分类号： G06F17/50
CPC分类号： H01L29/7841 , G06F17/5036
摘要： Procedures for SPICE parameter extraction, SPICE calculation, and device simulation for a partially depleted SOI MOSFET are provided. First, SPICE calculation parameters are set. At cthis time, parameters that describe the body current characteristics are not extracted but rather the body current is estimated to be zero. Then, in place of parameters that describe the body current characteristics, information regarding the steady state during circuit operation that is normally found from the body current characteristics, which is to say, the body charge and oscillation in the body potential, is treated as macro parameters that encompass information regarding the body current characteristics. After setting the parameters that include such macro parameters, a SPICE calculation for transient analysis is performed.
摘要翻译：提供了用于部分耗尽的SOI MOSFET的SPICE参数提取，SPICE计算和器件仿真的程序。首先，设置SPICE计算参数。在这个时候，描述体电流特性的参数不被提取，而是体电流估计为零。然后，代替描述体电流特性的参数，关于通常从身体电流特性（即身体电位的身体电荷和振荡）发现的电路操作期间的稳态的信息被视为宏包含关于身体电流特征的信息的参数。在设置包括这些宏参数的参数后，执行瞬态分析的SPICE计算。

7. 发明申请

US20050055191A1 Methods of extracting SPICE parameters, performing a spice calculation, and performing device simulation for a partially-depleted SOI MOSFET 失效
标题翻译：提取SPICE参数，执行香料计算以及对部分耗尽的SOI MOSFET执行器件仿真的方法
公开(公告)号：US20050055191A1
公开(公告)日：2005-03-10
申请号：US10720740
申请日：2003-11-24
申请人： Michiru Hogyoku
发明人： Michiru Hogyoku
IPC分类号： H01L29/786 , G06F17/50
CPC分类号： H01L29/7841 , G06F17/5036
摘要： Procedures for SPICE parameter extraction, SPICE calculation, and device simulation for a partially depleted SOI MOSFET are provided. First, SPICE calculation parameters are set. At this time, parameters that describe the body current characteristics are not extracted but rather the body current is estimated to be zero. Then, in place of parameters that describe the body current characteristics, information regarding the steady state during circuit operation that is normally found from the body current characteristics, which is to say, the body charge and oscillation in the body potential, is treated as macro parameters that encompass information regarding the body current characteristics. After setting the parameters that include such macro parameters, a SPICE calculation for transient analysis is performed.
摘要翻译：提供了用于部分耗尽的SOI MOSFET的SPICE参数提取，SPICE计算和器件仿真的程序。首先，设置SPICE计算参数。此时，不提取描述体电流特性的参数，而是估计体电流为零。然后，代替描述体电流特性的参数，关于通常从身体电流特性（即身体电位的身体电荷和振荡）发现的电路操作期间的稳态的信息被视为宏包含关于身体电流特征的信息的参数。在设置包括这些宏参数的参数后，执行瞬态分析的SPICE计算。

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