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1. 发明专利

JP2013118383A Semiconductor device, high electron mobility transistor, and method of transmitting electrons from source to drain through multiple channels 审中-公开
标题翻译：半导体器件，高电子移动晶体管，以及通过多个通道将电子从源极传输到漏极的方法
公开(公告)号：JP2013118383A
公开(公告)日：2013-06-13
申请号：JP2012264993
申请日：2012-12-04
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TEO KOON HOO , FENG PEIJIE , OISHI TOSHIYUKI , NAKAYAMA MASATOSHI , DUAN CHUNJIE
IPC分类号： H01L21/338 , H01L21/336 , H01L29/778 , H01L29/78 , H01L29/812
CPC分类号： H01L29/7783 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having channels containing a two-dimensional electron gas and inverted carriers.SOLUTION: A semiconductor device includes: a source 220 for transmitting electrons through channels; a drain 230 for receiving the electrons; a plurality of layers 270 for providing at least a part of the channels; and a gate 240 connected operationally to the plurality of layers for controlling the transmission of the electrons. The plurality of layers 270 includes an insulator layer 273, an N-surface layer 272, and a barrier layer 271, and these layers are selected so that the channels formed in the N-surface layer 272 contain a two-dimensional electron gas (2DEG) 210 and inverted carriers 211 during the operation of the semiconductor device.
摘要翻译：要解决的问题：提供一种具有包含二维电子气体和反向载流子的通道的半导体器件。解决方案：半导体器件包括：用于通过沟道传输电子的源220; 用于接收电子的漏极230; 多个层270，用于提供至少一部分通道; 以及可操作地连接到多个层的控制电子传输的门240。多个层270包括绝缘体层273，N表面层272和阻挡层271，并且这些层被选择为使得形成在N面层272中的沟道包含二维电子气（2DEG ）210和反相载体211。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2012205246A Harmonic processing circuit, high frequency amplifier and high frequency oscillator 审中-公开
标题翻译：谐波加工电路，高频放大器和高频振荡器
公开(公告)号：JP2012205246A
公开(公告)日：2012-10-22
申请号：JP2011070439
申请日：2011-03-28
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA HIROSHI , KIMURA SANETO , YAMANAKA KOJI , OISHI TOSHIYUKI , KUWATA EIGO , NAKAYAMA MASATOSHI
IPC分类号： H03F3/60
摘要： PROBLEM TO BE SOLVED: To solve the problem wherein second harmonic matching cannot be performed over a wideband and the frequency range of high efficiency is limited.SOLUTION: A harmonic processing circuit includes: a main line comprising a transmission line 2; a sub line in parallel connection to the main line comprising a circuit of a resistance 6 and transmission lines 5, 7 connected in series; and open stubs 3, 4 each having one end connected to a junction of the main line and the sub line.
摘要翻译：要解决的问题：为了解决不能在宽带上进行二次谐波匹配的问题，并且高效率的频率范围受到限制。谐波处理电路包括：主线，包括传输线2; 与主线并联连接的副线，包括电阻6和串联连接的传输线5,7的电路; 以及开口短截线3,4，每个短截线3,4的一端连接到主线和子线的连接处。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2010182854A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010182854A
公开(公告)日：2010-08-19
申请号：JP2009024683
申请日：2009-02-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NANJO TAKUMA , IMAI AKIFUMI , FUKITA MUNEYOSHI , ABE YUJI , OISHI TOSHIYUKI
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To solve such a problem that in a heterojunction field-effect transistor formed of a nitride semiconductor, forming a cap layer of 50 nm or larger on a barrier layer without reducing a two-dimensional electron gas concentration requires silicon doping at a high concentration of about 1×10
19 cm
-2 , but uniform doping with the silicon of such a high concentration is difficult due to the presence of a donor unintendedly coming into the nitride semiconductor during the epitaxial growth of oxygen or nitride cavities, etc., thus making difficult to control a doping concentration through the silicon only.
SOLUTION: An area closer to a barrier layer 40 that is subjected to the effect of polarization occurring as a result of heterojunction formation in a cap layer 50 is doped with a plurality of donors at a total concentration as high as the concentration of a two-dimensional electron gas, the donors forming an energy level higher than the Fermi level determined by the effect of polarization in a band gap of a nitride semiconductor making up the cap layer 50.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题为了解决在氮化物半导体形成的异质结场效应晶体管中，在阻挡层上形成50nm以上的覆盖层而不降低二维电子气体浓度的问题，需要由于存在一个供体，难以用高浓度的硅掺杂高浓度的硅，因此掺杂浓度高达1×10 20 / 在氧或氮化物空穴等的外延生长期间非常意外地进入氮化物半导体，从而难以控制仅通过硅的掺杂浓度。解决方案：在覆盖层50中由于异质结形成而产生极化作用的接近阻挡层40的区域掺杂有多个供体，其总浓度为二维电子气，供体形成的能级高于由构成盖层50的氮化物半导体的带隙中的偏振效应确定的费米能级。（C）2010，JPO＆INPIT

4. 发明专利

JP2010098221A Method of manufacturing nitride semiconductor device and method of manufacturing nitride semiconductor laser device 审中-公开
标题翻译：制造氮化物半导体器件的方法和制造氮化物半导体激光器件的方法
公开(公告)号：JP2010098221A
公开(公告)日：2010-04-30
申请号：JP2008269474
申请日：2008-10-20
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SHIOZAWA KATSUOMI , KANEMOTO KYOZO , OISHI TOSHIYUKI
IPC分类号： H01S5/323 , H01S5/042
摘要： PROBLEM TO BE SOLVED: To form a low-resistance and stable p-type electrode without a defect of contact between a semiconductor layer and an electrode material.
SOLUTION: A method of manufacturing a nitride semiconductor device includes performing plasma treatment onto a surface of a nitride semiconductor layer 1, that is a layer to be treated, and performing alkali treatment onto an amorphous layer 2, that is formed by the plasma treatment, to form a treatment plane suitable for ohmic contact formation in a case where an electrode is formed.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：形成低电阻且稳定的p型电极，而半导体层和电极材料之间没有接触缺陷。解决方案：一种制造氮化物半导体器件的方法包括：在作为被处理层的氮化物半导体层1的表面上进行等离子体处理，对由非晶层2形成的非晶质层2进行碱处理在形成电极的情况下形成适于欧姆接触形成的处理平面。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2010080493A Nitride semiconductor device, and method of manufacturing the same 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：JP2010080493A
公开(公告)日：2010-04-08
申请号：JP2008244092
申请日：2008-09-24
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： FUKITA MUNEYOSHI , NANJO TAKUMA , IMAI AKIFUMI , OISHI TOSHIYUKI , ABE YUJI
IPC分类号： H01L21/338 , H01L21/28 , H01L29/423 , H01L29/49 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a nitride semiconductor device which is good in response characteristics, can improve the problem of current collapse, and also can form a gate recess portion exactly equal to device design values with good reproducibility. SOLUTION: The nitride semiconductor device has a channel layer 2 formed on a substrate 1 and made of a first nitride semiconductor, a first electron supply layer 3a formed above the channel layer 2 and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor, and a second electron supply layer 3b formed as two isolated regions above the first electron supply layer and made of a third nitride semiconductor having the same band gap with or a larger band gap than the first nitride semiconductor. An etching stopper layer 4 made of a material having a slower dry etching speed than the second electron supply layer 3b is formed between the first and second electron supply layers 3a and 3b, and a gate electrode 5 is formed filling the gate recess portion sandwiched between two regions above the layer 4. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供响应特性良好的氮化物半导体器件，可以改善电流崩溃的问题，并且还可以形成具有良好再现性的与设计值完全相等的栅极凹部。解决方案：氮化物半导体器件具有形成在衬底1上并由第一氮化物半导体制成的沟道层2，形成在沟道层2上方并由具有较大带的第二氮化物半导体形成的第一电子供应层3a 间隙比第一氮化物半导体形成，第二电子供给层3b形成为第一电子供给层上方的两个隔离区域，并且由与第一氮化物半导体具有相同带隙或更大带隙的第三氮化物半导体形成。在第一和第二电子供给层3a和3b之间形成有由比第二电子供给层3b慢的干蚀刻速度的材料制成的蚀刻阻挡层4，并且形成一个栅极电极5，版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2009158745A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009158745A
公开(公告)日：2009-07-16
申请号：JP2007335698
申请日：2007-12-27
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TARUI YOICHIRO , OTSUKA KENICHI , SUZUKI YOSUKE , SHIOZAWA KATSUOMI , KANEMOTO KYOZO , OISHI TOSHIYUKI , TOKUDA YASUKI , OMORI TATSUO
IPC分类号： H01L21/28 , H01S5/323
CPC分类号： H01L21/28575 , H01L29/2003 , H01L33/0095 , H01L33/32 , H01L33/40
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can reduce the contact resistance of an ohmic electrode to a p-type nitride semiconductor layer, and can achieve long-term stable operation.
SOLUTION: In an electrode forming step, in forming a p-type ohmic electrode composed of a metal film comprising a Pd film and a Ta film by successive lamination of the Pd film which is a first p-type ohmic electrode 10 and the Ta film which is a second p-type ohmic electrode 11 on a p-type GaN contact layer 7, the metal film is formed to include an oxygen atom. Thus, in the presence of an oxygen atom in the metal film, then in a heat-treatment step, the p-type ohmic electrode composed of the metal film is heat-treated in an atmosphere that contains no oxygen atom-containing gas.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以将欧姆电极的接触电阻降低到p型氮化物半导体层的半导体器件的制造方法，并且可以实现长期稳定的操作。解决方案：在电极形成步骤中，通过连续层压作为第一p型欧姆电极10的Pd膜和形成由Pd膜和Ta膜构成的金属膜的p型欧姆电极，作为p型GaN接触层7上的第二p型欧姆电极11的Ta膜，形成包含氧原子的金属膜。因此，在金属膜中存在氧原子的情况下，在热处理工序中，将由金属膜构成的p型欧姆电极在不含氧原子气体的气氛中进行热处理。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2006147914A Nitride semiconductor device and its manufacturing method 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：JP2006147914A
公开(公告)日：2006-06-08
申请号：JP2004337282
申请日：2004-11-22
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SHIOZAWA KATSUOMI , OISHI TOSHIYUKI , KAWASAKI KAZUE , ABE YUJI
IPC分类号： H01L21/28 , H01L33/32 , H01L33/40
CPC分类号： H01L21/28575 , H01L33/32 , H01L33/40
摘要： PROBLEM TO BE SOLVED: To provide a nitride semiconductor device being capable of reducing a contact resistance between a p-type contact layer and a p-type electrode and having the p-type electrode. SOLUTION: P-type electrode materials are formed on the top face of the p-type contact layer 1. The p-type electrode materials are composed of an AuGa film 2, an Au film 3, a Pt film 4, and the Au film 5. The AuGa film 2 is formed on the p-type contact layer 1. The Au film 3 is formed on the AuGa film 2. The Pt film 4 is formed on the Au film 3. The Au film 5 is formed on the Pt film 4. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供能够降低p型接触层和p型电极之间并具有p型电极的接触电阻的氮化物半导体器件。解决方案：P型电极材料形成在p型接触层1的顶面上.p型电极材料由AuGa膜2，Au膜3，Pt膜4和 Au膜5.在p型接触层1上形成AuGa膜2.在AuGa膜2上形成Au膜3.在Au膜3上形成Pt膜4.形成Au膜5 在Pt膜4上。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2004095640A Semiconductor device and its manufacturing method 有权
公开(公告)号：JP2004095640A
公开(公告)日：2004-03-25
申请号：JP2002251272
申请日：2002-08-29
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OISHI TOSHIYUKI , MIURA NARIHISA , ABE YUJI , FUKITA MUNEYOSHI , NANJO TAKUMA
IPC分类号： H01L21/76 , H01L21/265 , H01L21/338 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device which has a crystal layer formed of a nitride semiconductor and also has a high-resistance separation element region.
SOLUTION: The semiconductor device is configured to have the high-resistance region 7 formed in crystal layers 2 and 3 formed of nitride semiconductors by injecting ions of ≥20C group II atoms.
COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2003282479A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003282479A
公开(公告)日：2003-10-03
申请号：JP2002088485
申请日：2002-03-27
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OISHI TOSHIYUKI , MIURA NARIHISA , ABE YUJI , FUKITA MUNEYOSHI , NANJO TAKUMA , TAKAMI TETSUYA
IPC分类号： H01L21/28 , H01L21/338 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, which has superior performance by suppressing the formation of high-resistance alloys on electrode provided in contact with a nitride semiconductor by reaction between a layer containing Au and a layer containing Al, and a method for manufacturing the same.
SOLUTION: The electrodes 5 and 6 including the layer 11 containing Au and the layer 9 containing Al are provided in contact with the nitride semiconductor 3 and a metal layer 10 of ≥2,000°C in fusion point is interposed between the layer 11 containing Au and the layer 9 containing Al.
COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2014220751A 高調波処理回路有权
标题翻译：谐波加工电路
公开(公告)号：JP2014220751A
公开(公告)日：2014-11-20
申请号：JP2013100391
申请日：2013-05-10
申请人：三菱電機株式会社 , Mitsubishi Electric Corp
发明人： KOSAKA NAOKI , YAMAGUCHI YUTARO , KOMARU RYUTA , KUWATA EIGO , MAEHARA HIROAKI , OTSUKA HIROSHI , UCHIDA HIROMITSU , OISHI TOSHIYUKI , YAMANAKA KOJI , TARUI YUKINORI , KIMURA MAKOTO
IPC分类号： H03F3/60
CPC分类号： H03F3/60
摘要：【課題】外部負荷の2倍波反射係数に対する2倍波負荷インピーダンスへの影響を小さく抑え、効率の低下を抑制し、ロバストかつ広帯域性を実現する高調波処理回路を得る。【解決手段】FET1のゲートに接続され、線路長(λ/4+α@2fo)を有する伝送線路2と、伝送線路2のFET1側に接続され、線路長(
摘要翻译：要解决的问题：提供一种谐波处理电路，其通过相对于外部负载的二次反射系数减小对二次负载阻抗的影响来实现鲁棒且宽带特性，并且抑制效率的降低。解决方案：谐波处理电路包括：连接到FET1的栅极并且具有（λ/ 4 +α@ 2fo）的线路长度的传输线2; 连接在传输线2侧与FET 1并具有（<λ/ 4 @ 2fo）的线路长度的传输线3; 连接在与FET1相反的传输线2侧并具有（λ/ 4 @ 2fo）的线长的传输线4; 以及连接在传输线2和传输线路4之间的电阻器5.这可以降低对外部的二阶反射系数＆Ggr; L（2fo）对二阶负载阻抗＆Ggr; fet（2fo）的影响加载并抑制效率的降低，以实现鲁棒和宽带特性。

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