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1. 发明授权

US06528432B1 H2-or H2/N2-plasma treatment to prevent organic ILD degradation 有权
标题翻译： H2或H2 / N2等离子体处理以防止有机ILD降解
公开(公告)号：US06528432B1
公开(公告)日：2003-03-04
申请号：US09729455
申请日：2000-12-05
申请人： Minh Van Ngo , Dawn Hopper , Robert A. Huertas
发明人： Minh Van Ngo , Dawn Hopper , Robert A. Huertas
IPC分类号： H01L214763
CPC分类号： H01L23/5329 , H01L21/31058 , H01L21/76826 , H01L21/76829 , H01L2924/0002 , H01L2924/00
摘要： Degradation of organic low-k interlayer dielectrics during fabrication is substantially prevented or significantly reduced by treatment with a H2- or H2/N2-containing plasma. Embodiments include treating a SiCOH, such as Black Diamond®, ILD with an H2 or H2/N2 plasma after deposition, after forming a damascene opening therein and/or after CMP but prior to capping layer deposition.
摘要翻译：通过用含H2或H2 / N2的等离子体处理，可以显着地防止或显着降低制造过程中有机低k层间电介质的退化。实施方案包括在沉积之后，在其中形成镶嵌开口和/或CMP之后，但在覆盖层沉积之前，用H 2或H 2 / N 2等离子体处理SiCOH，例如Black Diamond，ILD。

2. 发明授权

US06686232B1 Ultra low deposition rate PECVD silicon nitride 有权
标题翻译：超低沉积速率PECVD氮化硅
公开(公告)号：US06686232B1
公开(公告)日：2004-02-03
申请号：US10173717
申请日：2002-06-19
申请人： Minh Van Ngo , Robert A. Huertas , Dawn Hopper , Hieu Pham
发明人： Minh Van Ngo , Robert A. Huertas , Dawn Hopper , Hieu Pham
IPC分类号： H01L21471
CPC分类号： H01L29/6659 , C23C16/345 , H01L21/3185 , H01L29/6656
摘要： A thin silicon nitride layer is deposited at an ultra low deposition rate by PECVD by reducing the NH3 flow rate and/or reducing the SiH4 flow rate. Embodiments include depositing a thin layer of silicon nitride, e.g., 100 Å or less, on a thin silicon oxide liner over a gate electrode, at an NH3 flow rate of 100 to 800 sccm, a SiH4 flow rate of 50 to 100 sccm and a reduced pressure of 0.8 to 1.8 Torr. Embodiments of the present invention further include depositing the silicon nitride layer in multiple deposition stages, e.g., depositing the silicon nitride layer in five deposition stages of 20 Å each.
摘要翻译：通过减少NH 3流速和/或降低SiH 4流速，通过PECVD以超低沉积速率沉积薄的氮化硅层。实施例包括在栅电极上的薄氧化硅衬垫上以100至800sccm的NH 3流速，50至100sccm的SiH 4流率和50至100sccm的SiH 4流速沉积例如100或更小的氮化硅薄层 0.8〜1.8乇减压。本发明的实施例还包括在多个沉积阶段中沉积氮化硅层，例如，将氮化硅层沉积在各自的五个沉积阶段中。

3. 发明授权

US06562416B2 Method of forming low resistance vias 有权
公开(公告)号：US06562416B2
公开(公告)日：2003-05-13
申请号：US09846187
申请日：2001-05-02
申请人： Minh Van Ngo , Robert A. Huertas , Dawn Hopper
发明人： Minh Van Ngo , Robert A. Huertas , Dawn Hopper
IPC分类号： C23C1402
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76807
摘要： Low resistant vias are formed by sequentially treating an opening in an interlayer dielectric and the exposed surface of a lower metal feature with an NH3 plasma followed by a N2/H2 plasma, thereby removing any oxide on the metal surface and removing residual polymers or polymeric deposits generated during etching to form the opening. Embodiments include forming a dual damascene opening in a low-k interlayer dielectric exposing the upper surface of a lower Cu or Cu alloy feature, sequentially treating the opening and the upper surface of the lower metal feature with an NH3 plasma and then with a N2/H2 plasma, Ar sputter etching, depositing a barrier layer lining the opening, depositing a seedlayer and filling the opening with Cu or a Cu alloy.

4. 发明授权

US06596631B1 Method of forming copper interconnect capping layers with improved interface and adhesion 有权
标题翻译：形成具有改善界面和粘合性的铜互连封盖层的方法
公开(公告)号：US06596631B1
公开(公告)日：2003-07-22
申请号：US09626455
申请日：2000-07-26
申请人： Minh Van Ngo , Hartmut Ruelke , Lothar Mergili , Joerg Hohage , Lu You , Robert A. Huertas , Richard J. Huang
发明人： Minh Van Ngo , Hartmut Ruelke , Lothar Mergili , Joerg Hohage , Lu You , Robert A. Huertas , Richard J. Huang
IPC分类号： H01L244
CPC分类号： H01L21/76883 , H01L21/76834 , Y10S438/913
摘要： The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.
摘要翻译：通过在处理暴露的平坦化表面之后延迟和/或缓慢地升高硅烷的引入以沉积氮化硅覆盖层来显着增强界面的完整性和阻挡层或覆盖层与Cu或Cu合金互连构件之间的粘合性具有含氨等离子体的Cu或Cu合金。其他实施方案包括在升高的温度下用氮气吹扫反应室以在引入用于等离子体处理的晶片之前去除残留气体。

5. 发明授权

US06388330B1 Low dielectric constant etch stop layers in integrated circuit interconnects 有权
标题翻译：集成电路互连中的低介电常数蚀刻停止层
公开(公告)号：US06388330B1
公开(公告)日：2002-05-14
申请号：US09776012
申请日：2001-02-01
申请人： Minh Van Ngo , Dawn M. Hopper , Robert A. Huertas , Terri J. Kitson
发明人： Minh Van Ngo , Dawn M. Hopper , Robert A. Huertas , Terri J. Kitson
IPC分类号： H01L2348
CPC分类号： H01L23/5222 , H01L21/76801 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method of manufacture therefore is provided having a semiconductor substrate with a semiconductor device with a dielectric layer over the semiconductor substrate. A conductor core fills the opening in the dielectric layer. An etch stop layer with a dielectric constant below 5.5 is formed over the first dielectric layer and conductor core. A second dielectric layer over the etch stop layer has an opening provided to the conductor core. A second conductor core fills the second opening and is connected to the first conductor core.
摘要翻译：因此，提供了具有半导体衬底和半导体器件的集成电路和制造方法，所述半导体衬底具有半导体衬底上的介电层。导体芯填充电介质层中的开口。在第一介电层和导体芯上形成介电常数低于5.5的蚀刻停止层。蚀刻停止层上的第二电介质层具有提供给导体芯的开口。第二导体芯填充第二开口并连接到第一导体芯。

6. 发明授权

US07300886B1 Interlayer dielectric for charge loss improvement 有权
标题翻译：用于电荷损耗改善的层间电介质
公开(公告)号：US07300886B1
公开(公告)日：2007-11-27
申请号：US11147208
申请日：2005-06-08
申请人： Minh Van Ngo , Ning Cheng , Wenmei Li , Angela T. Hui , Pei-Yuan Gao , Robert A. Huertas
发明人： Minh Van Ngo , Ning Cheng , Wenmei Li , Angela T. Hui , Pei-Yuan Gao , Robert A. Huertas
IPC分类号： H01L21/31
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02271 , H01L27/115 , H01L27/11568
摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.
摘要翻译：一种制造存储器件的方法包括在衬底上形成第一介电层，并在第一介电层上形成电荷存储元件。该方法还包括在电荷存储元件上形成第二电介质层，并在第二电介质层上形成控制栅极。该方法还包括在高温下在控制栅极上沉积层间电介质。

7. 发明授权

US06383880B1 NH3/N2-plasma treatment for reduced nickel silicide bridging 有权
标题翻译： NH3 / N2等离子体处理用于还原硅化镍桥接
公开(公告)号：US06383880B1
公开(公告)日：2002-05-07
申请号：US09679374
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Robert A. Huertas
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Robert A. Huertas
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/3105
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen to create a clean surface region having increased nitrogen. Embodiments include treating the silicon nitride sidewall spacers with an ammonia and nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译：通过用包含氨和氮的等离子体处理氮化硅侧壁间隔物的暴露表面以产生具有增加的氮的清洁表面区域来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源/漏区之间的桥接。实施例包括用氨和氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

8. 发明授权

US07023046B2 Undoped oxide liner/BPSG for improved data retention 有权
标题翻译：未掺杂氧化物衬垫/ BPSG，以改善数据保留
公开(公告)号：US07023046B2
公开(公告)日：2006-04-04
申请号：US10617450
申请日：2003-07-11
申请人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
发明人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/31612 , H01L21/31625 , H01L27/115 , H01L29/511
摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.
摘要翻译：具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在相同的沉积室。

9. 发明授权

US06809043B1 Multi-stage, low deposition rate PECVD oxide 有权
标题翻译：多级，低沉积速率PECVD氧化物
公开(公告)号：US06809043B1
公开(公告)日：2004-10-26
申请号：US10173611
申请日：2002-06-19
申请人： Minh Van Ngo , Robert A. Huertas , Hieu Pham
发明人： Minh Van Ngo , Robert A. Huertas , Hieu Pham
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28247 , H01L21/3144 , H01L21/3145 , H01L21/31612
摘要： A silicon oxide layer is deposited at a thickness of about 50 Å or less by a multi-stage method comprising depositing a sub-layer of silicon oxide in each stage by PECVD at a low deposition rate. Embodiments include depositing a silicon dioxide liner over a gate electrode in at least four stages, each stage comprising depositing a sub-layer at a thickness of 10 Å or less.
摘要翻译：氧化硅层通过多级方法沉积在大约等于或小于50埃的厚度，包括通过PECVD以低沉积速率在每个阶段沉积氧化硅的子层。实施例包括在至少四个阶段中在栅电极上沉积二氧化硅衬垫，每个阶段包括沉积厚度为或更小的子层。

10. 发明授权

US6143672A Method of reducing metal voidings in 0.25 .mu.m AL interconnect 失效
标题翻译：在0.25微米AL互连中减少金属空隙的方法
公开(公告)号：US6143672A
公开(公告)日：2000-11-07
申请号：US084442
申请日：1998-05-22
申请人： Minh Van Ngo , Simon S. Chan , Suzette K. Pangrle , Robert A. Huertas
发明人： Minh Van Ngo , Simon S. Chan , Suzette K. Pangrle , Robert A. Huertas
IPC分类号： C23C16/40 , H01L21/316 , H01L21/768 , H01L21/76 , H01L21/469
CPC分类号： H01L21/02164 , C23C16/402 , H01L21/02211 , H01L21/02274 , H01L21/31608 , H01L21/76801
摘要： In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an aluminum alloy layer; depositing the dielectric layer over the stacked interconnect structureunder a pressure from about 1 mTorr to about 6 mTorr, an O.sub.2 flow rate from about 110 sccm to about 130 sccm and a silane flow rate from about 52 sccm to about 60 sccm at a bias power from about 2500 W to about 3100 W,under a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 250 sccm to about 300 sccm at a power from about 900 W to about 1300 W at a temperature from about 300.degree. C. to about 350.degree. C., orunder a pressure from about 2 Torr to about 2.8 Torr, an N.sub.2 flow rate from about 7 l to about 11.5 l, an N.sub.2 O flow rate from about 1 l to about 2 l and a silane flow rate from about 80 sccm to about 120 sccm at a power from about 900 W to about 1300 W at a temperature from about 390.degree. C. to about 410.degree. C.
摘要翻译：在一个实施例中，本发明涉及一种在堆叠的互连结构上沉积电介质层的方法，其包括以下步骤：提供具有至少一个堆叠互连结构的衬底，所述堆叠互连结构包括铝层和铝合金层中的至少一个 ; 在约1mTorr至约6mTorr的压力下，将电介质层沉积在堆叠的互连结构上，O 2流速为约110sccm至约130sccm，硅烷流速为约52sccm至约60sccm，偏置功率约2500W至约3100W，在约2托至约2.8托的压力下，N 2流速为约7升至约11.5升，N 2 O流速为约1升至约2升，硅烷流量在约300至约350℃的温度或约2托至约2.8托的压力下以约900至约1300瓦的功率从约250sccm至约300sccm的速率， N 2流速为约7升至约11.5升，N 2 O流速为约1升至约2升，硅烷流速为约80sccm至约120sccm，功率为约900W至约1300W，温度约390℃至约410℃

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