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1. 发明授权

US08815744B2 Technique for controlling trench profile in semiconductor structures 有权
标题翻译：用于控制半导体结构中的沟槽轮廓的技术
公开(公告)号：US08815744B2
公开(公告)日：2014-08-26
申请号：US12109302
申请日：2008-04-24
申请人： Hui Chen , Qi Wang , Briant Harward , James Pan
发明人： Hui Chen , Qi Wang , Briant Harward , James Pan
IPC分类号： H01L21/311
CPC分类号： H01L21/3065 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.
摘要翻译：一种形成半导体结构的方法包括以下步骤。在半导体区域中使用掩模层形成沟槽，使得沟槽具有第一深度，沿其底部的第一宽度和具有第一斜率的侧壁。去除掩模层，并且执行斜面蚀刻以使沟槽的侧壁逐渐变细，使得侧壁具有小于第一斜率的第二斜率。

2. 发明授权

US08772169B2 Technique for controlling trench profile in semiconductor structures 有权
公开(公告)号：US08772169B2
公开(公告)日：2014-07-08
申请号：US12109302
申请日：2008-04-24
申请人： Hui Chen , Qi Wang , Briant Harward , James Pan
发明人： Hui Chen , Qi Wang , Briant Harward , James Pan
IPC分类号： H01L21/311
摘要： A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

3. 发明申请

US20090269896A1 Technique for Controlling Trench Profile in Semiconductor Structures 有权
标题翻译：控制半导体结构中沟槽剖面的技术
公开(公告)号：US20090269896A1
公开(公告)日：2009-10-29
申请号：US12109302
申请日：2008-04-24
申请人： Hui Chen , Qi Wang , Briant Harward , James Pan
发明人： Hui Chen , Qi Wang , Briant Harward , James Pan
IPC分类号： H01L21/336
CPC分类号： H01L21/3065 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.
摘要翻译：一种形成半导体结构的方法包括以下步骤。在半导体区域中使用掩模层形成沟槽，使得沟槽具有第一深度，沿其底部的第一宽度和具有第一斜率的侧壁。去除掩模层，并且执行斜面蚀刻以使沟槽的侧壁逐渐变细，使得侧壁具有小于第一斜率的第二斜率。

4. 发明申请

US20090302482A1 Structure and Method for Forming Hybrid Substrate 有权
标题翻译：用于形成混合基板的结构和方法
公开(公告)号：US20090302482A1
公开(公告)日：2009-12-10
申请号：US12332326
申请日：2008-12-10
申请人： Qi Wang , Joelle Sharp , Minhua Li , Hui Chen
发明人： Qi Wang , Joelle Sharp , Minhua Li , Hui Chen
IPC分类号： H01L25/16 , H01L21/78
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L29/7802 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A first and a second substrate are bonded together to thereby form a unitary hybrid substrate. Predefined portions of the first substrate are removed to form openings in the first substrate through which surface regions of the second substrate are exposed. A selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates is carried out to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate. The epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate.
摘要翻译：将第一基板和第二基板接合在一起形成单一的混合基板。去除第一衬底的预定部分以在第一衬底中形成开口，第二衬底的表面区域暴露在第一衬底中。执行相对于第一和第二衬底的晶体取向选择性的选择性外延生长工艺，从而从第二衬底的暴露表面形成外延硅，但不从第一衬底的暴露表面形成外延硅。由第二衬底的暴露表面形成的外延硅具有与第二衬底相同的晶体取向。

5. 发明授权

US08039401B2 Structure and method for forming hybrid substrate 有权
标题翻译：用于形成混合基板的结构和方法
公开(公告)号：US08039401B2
公开(公告)日：2011-10-18
申请号：US12332326
申请日：2008-12-10
申请人： Qi Wang , Joelle Sharp , Minhua Li , Hui Chen
发明人： Qi Wang , Joelle Sharp , Minhua Li , Hui Chen
IPC分类号： H01L21/30 , H01L21/46 , H01L21/20 , H01L21/36 , H01L21/311
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L29/7802 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A first and a second substrate are bonded together to thereby form a unitary hybrid substrate. Predefined portions of the first substrate are removed to form openings in the first substrate through which surface regions of the second substrate are exposed. A selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates is carried out to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate. The epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate.
摘要翻译：将第一基板和第二基板接合在一起形成单一的混合基板。去除第一衬底的预定部分，以在第一衬底中形成开口，第二衬底的表面区域暴露在第一衬底中。执行相对于第一和第二衬底的晶体取向选择性的选择性外延生长工艺，从而从第二衬底的暴露表面形成外延硅，但不从第一衬底的暴露表面形成外延硅。由第二衬底的暴露表面形成的外延硅具有与第二衬底相同的晶体取向。

6. 发明申请

US20110012174A1 Structure and Method for Forming Field Effect Transistor with Low Resistance Channel Region 有权
标题翻译：用于形成具有低电阻通道区域的场效应晶体管的结构和方法
公开(公告)号：US20110012174A1
公开(公告)日：2011-01-20
申请号：US12891616
申请日：2010-09-27
申请人： James Pan , Qi Wang
发明人： James Pan , Qi Wang
IPC分类号： H01L29/06 , H01L21/335
CPC分类号： H01L29/165 , H01L21/26506 , H01L29/407 , H01L29/42368 , H01L29/66712 , H01L29/66719 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7813
摘要： A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction.
摘要翻译：沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。每个体区与硅区形成PN结。栅极电介质层至少在每个沟槽的上侧壁布线，并且使栅电极与身体区域绝缘。第一导电体的源区在沟槽的侧面。硅 - 锗区域垂直延伸穿过每个源极区域并穿过对应的主体区域，并且在到达PN结点之前终止于相应的体区域内。

7. 发明授权

US07943993B2 Structure and method for forming field effect transistor with low resistance channel region 有权
标题翻译：用于形成具有低电阻通道区域的场效应晶体管的结构和方法
公开(公告)号：US07943993B2
公开(公告)日：2011-05-17
申请号：US12891616
申请日：2010-09-27
申请人： James Pan , Qi Wang
发明人： James Pan , Qi Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/165 , H01L21/26506 , H01L29/407 , H01L29/42368 , H01L29/66712 , H01L29/66719 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7813
摘要： A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction.
摘要翻译：沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。每个体区与硅区形成PN结。栅极电介质层至少在每个沟槽的上侧壁布线，并且使栅电极与身体区域绝缘。沟槽侧面的第一导电体的源极区域。硅 - 锗区域垂直延伸穿过每个源极区域并穿过对应的主体区域，并且在到达PN结点之前终止于相应的体区域内。

8. 发明授权

US08278686B2 Structure and method for forming planar gate field effect transistor with low resistance channel region 有权
标题翻译：用于形成具有低电阻通道区域的平面栅极场效应晶体管的结构和方法
公开(公告)号：US08278686B2
公开(公告)日：2012-10-02
申请号：US13103728
申请日：2011-05-09
申请人： James Pan , Qi Wang
发明人： James Pan , Qi Wang
IPC分类号： H01L29/10 , H01L29/786 , H01L21/28
CPC分类号： H01L29/165 , H01L21/26506 , H01L29/407 , H01L29/42368 , H01L29/66712 , H01L29/66719 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7813
摘要： A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.
摘要翻译：垂直导电的平面栅极场效应晶体管包括第一导电类型的硅区域，在硅区域上延伸的硅 - 锗层，横向延伸但与硅 - 锗层绝缘的栅电极，主体区域在硅 - 锗层和硅区域中延伸的第二导电类型以及在硅 - 锗层中延伸的第一导电类型的源极区域。栅极电极横向重叠源极和主体区域，使得在源极区域和主体区域的外边界之间直接在栅电极下方延伸的硅锗层的一部分形成沟道区域。

9. 发明申请

US20110215377A1 Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region 有权
标题翻译：用于形成具有低电阻通道区域的平面栅场效应晶体管的结构和方法
公开(公告)号：US20110215377A1
公开(公告)日：2011-09-08
申请号：US13103728
申请日：2011-05-09
申请人： James Pan , Qi Wang
发明人： James Pan , Qi Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/165 , H01L21/26506 , H01L29/407 , H01L29/42368 , H01L29/66712 , H01L29/66719 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7813
摘要： A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.
摘要翻译：垂直导电的平面栅极场效应晶体管包括第一导电类型的硅区域，在硅区域上延伸的硅 - 锗层，横向延伸但与硅 - 锗层绝缘的栅电极，主体区域在硅 - 锗层和硅区域中延伸的第二导电类型以及在硅 - 锗层中延伸的第一导电类型的源极区域。栅极电极横向重叠源极和主体区域，使得在源极区域和主体区域的外边界之间直接在栅电极下方延伸的硅锗层的一部分形成沟道区域。

10. 发明授权

US07825465B2 Structure and method for forming field effect transistor with low resistance channel region 有权
标题翻译：用于形成具有低电阻通道区域的场效应晶体管的结构和方法
公开(公告)号：US07825465B2
公开(公告)日：2010-11-02
申请号：US12330273
申请日：2008-12-08
申请人： James Pan , Qi Wang
发明人： James Pan , Qi Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/165 , H01L21/26506 , H01L29/407 , H01L29/42368 , H01L29/66712 , H01L29/66719 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7813
摘要： A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.
摘要翻译：沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。每个主体区域与硅区域形成第一PN结，并且每个主体区域包括在相邻沟槽之间横向延伸的第二导电类型的硅 - 锗层。第一导电体的源区在沟槽的侧面，并且每个源极区域与身体区域之一形成第二PN结。通道区域沿着源区域和身体区域的底表面之间的沟槽的侧壁在身体区域中延伸。硅 - 锗层延伸到相应的沟道区，从而降低沟道电阻。

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