专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120156845A1 METHOD OF FORMING A FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE 审中-公开
标题翻译：形成场效应晶体管和肖特基二极管的方法
公开(公告)号：US20120156845A1
公开(公告)日：2012-06-21
申请号：US13325047
申请日：2011-12-13
申请人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
发明人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L21/26586 , H01L27/0629 , H01L29/0619 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7828 , H01L29/872 , H01L2924/13091
摘要： A method for forming a field effect transistor and Schottky diode includes forming a well region in a first portion of a silicon region where the field effect transistor is to be formed but not in a second portion of the silicon region where the Schottky diode is to be formed. Gate trenches are formed extending into the silicon region. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. Exposed surfaces of the well region are recessed to form a recess between every two adjacent trenches. Without masking any portion of the active area, a zero-degree blanket implant is performed to form a heavy body region of the second conductivity type in the well region between every two adjacent trenches.
摘要翻译：用于形成场效应晶体管和肖特基二极管的方法包括在要形成场效应晶体管的硅区域的第一部分中形成阱区，但在肖特基二极管的硅区域的第二部分中不形成阱区形成。形成延伸到硅区域的栅极沟槽。在每个栅极沟槽中形成凹陷栅极。在每个凹入的栅极上形成电介质盖。井区域的露出表面是凹进的，以在每两个相邻沟槽之间形成一个凹槽。在不掩蔽有效区域的任何部分的情况下，执行零度覆盖植入以在每两个相邻沟槽之间的阱区域中形成第二导电类型的重体区域。

2. 发明申请

US20090111227A1 Method for Forming Trench Gate Field Effect Transistor with Recessed Mesas Using Spacers 有权
标题翻译：使用隔板形成具有嵌入式台面的沟槽栅场效应晶体管的方法
公开(公告)号：US20090111227A1
公开(公告)日：2009-04-30
申请号：US12346626
申请日：2008-12-30
申请人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
发明人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L21/26586 , H01L27/0629 , H01L29/0619 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7828 , H01L29/872 , H01L2924/13091
摘要： A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region. The second silicon region is recessed through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain. The remaining portions of the second silicon region form source regions.
摘要翻译：用于形成具有有源区和围绕有源区的端接区的场效应晶体管的方法包括在阱区和第一硅区具有相反导电类型的第一硅区中形成阱区。形成延伸穿过阱区并终止在第一硅区内的栅极沟槽。在每个栅极沟槽中形成凹陷栅极。在每个凹入的栅极上形成电介质盖。阱区域在相邻沟槽之间凹陷以暴露每个电介质盖的上侧壁。进行覆盖源植入以在每两个相邻沟槽之间的凹陷区域的上部中形成第二硅区域。沿着电介质盖的每个暴露的上侧壁形成介电间隔物，每两个相邻的电介质间隔物位于每两个相邻栅极沟槽之间，形成在第二硅区上的开口。第二硅区域在每两个相邻的电介质间隔物之间通过开口凹进，使得只有介电间隔物正下方的第二硅区域的部分保留。第二硅区域的剩余部分形成源区域。

3. 发明授权

US08686493B2 High density FET with integrated Schottky 有权
标题翻译：集成肖特基的高密度FET
公开(公告)号：US08686493B2
公开(公告)日：2014-04-01
申请号：US12242633
申请日：2008-09-30
申请人： Paul Thorup , Christopher Lawrence Rexer
发明人： Paul Thorup , Christopher Lawrence Rexer
IPC分类号： H01L29/66
CPC分类号： H01L29/66734 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/47 , H01L29/66727 , H01L29/7806
摘要： A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.
摘要翻译：半导体结构包括单片集成沟槽FET和肖特基二极管。半导体结构还包括延伸到半导体区域中的多个沟槽。在每个沟槽中设置一叠栅极和屏蔽电极。主体区域在相邻沟槽之间的半导体区域上延伸，源区域在每个主体区域上延伸。具有锥形边缘的凹槽在两个相邻沟槽的每两个相邻的沟槽之间延伸穿过本体区域的两个相邻沟槽的上角，并终止在身体区域下方的半导体区域中。互连层延伸到每个凹部中以电接触源区域和主体区域的锥形侧壁，并且沿着每个凹部的底部接触半导体区域以在它们之间形成肖特基接触。

4. 发明申请

US20090315083A1 Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices 有权
标题翻译：用于形成用于沟槽栅极器件的厚底电介质（TBD）的结构和方法
公开(公告)号：US20090315083A1
公开(公告)日：2009-12-24
申请号：US12143510
申请日：2008-06-20
申请人： James Pan , Christopher Lawrence Rexer
发明人： James Pan , Christopher Lawrence Rexer
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/8725
摘要： A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.
摘要翻译：包括沟槽栅极FET的半导体结构如下形成。使用掩模在半导体区域中形成多个沟槽。掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。沿每个沟槽的底部形成厚底部电介质（TBD）。第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。

5. 发明授权

US08669623B2 Structure related to a thick bottom dielectric (TBD) for trench-gate devices 有权
标题翻译：与沟槽栅极器件的厚底部电介质（TBD）有关的结构
公开(公告)号：US08669623B2
公开(公告)日：2014-03-11
申请号：US12870600
申请日：2010-08-27
申请人： James Pan , Christopher Lawrence Rexer
发明人： James Pan , Christopher Lawrence Rexer
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/8725
摘要： A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.
摘要翻译：包括屏蔽栅极的半导体结构如下形成。使用掩模在半导体区域中形成多个沟槽。掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。形成在每个沟槽的至少下侧壁延伸的屏蔽电介质。沿每个沟槽的底部形成厚底部电介质（TBD）。第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。屏蔽电极形成在每个沟槽的底部。在每个沟槽中的屏蔽电极之上形成栅电极。

6. 发明申请

US20100320534A1 Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices 有权
标题翻译：用于形成用于沟槽栅极器件的厚底电介质（TBD）的结构和方法
公开(公告)号：US20100320534A1
公开(公告)日：2010-12-23
申请号：US12870600
申请日：2010-08-27
申请人： James Pan , Christopher Lawrence Rexer
发明人： James Pan , Christopher Lawrence Rexer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/8725
摘要： A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.
摘要翻译：包括屏蔽栅极的半导体结构如下形成。使用掩模在半导体区域中形成多个沟槽。掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。形成在每个沟槽的至少下侧壁延伸的屏蔽电介质。沿每个沟槽的底部形成厚底部电介质（TBD）。第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。屏蔽电极形成在每个沟槽的底部。在每个沟槽中的屏蔽电极之上形成栅电极。

7. 发明授权

US08680611B2 Field effect transistor and schottky diode structures 有权
标题翻译：场效应晶体管和肖特基二极管结构
公开(公告)号：US08680611B2
公开(公告)日：2014-03-25
申请号：US13600184
申请日：2012-08-30
申请人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
发明人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
IPC分类号： H01L29/76
CPC分类号： H01L29/7827 , H01L21/26586 , H01L27/0629 , H01L29/0619 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7828 , H01L29/872 , H01L2924/13091
摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.
摘要翻译：根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。导体层可与半导体区形成肖特基接触。

8. 发明申请

US20120319197A1 FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES 有权
标题翻译：场效应晶体管和肖特基二极管结构
公开(公告)号：US20120319197A1
公开(公告)日：2012-12-20
申请号：US13600184
申请日：2012-08-30
申请人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
发明人： Christopher Boguslaw Kocon , Steven Sapp , Paul Thorup , Dean Probst , Robert Herrick , Becky Losee , Hamza Yilmaz , Christopher Lawrence Rexer , Daniel Calafut
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L21/26586 , H01L27/0629 , H01L29/0619 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7828 , H01L29/872 , H01L2924/13091
摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.
摘要翻译：根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。导体层可与半导体区形成肖特基接触。

9. 发明授权

US07586156B2 Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device 有权
标题翻译：宽带隙器件与具有比宽带隙器件更低的雪崩击穿电压和更高的正向压降的器件并联
公开(公告)号：US07586156B2
公开(公告)日：2009-09-08
申请号：US11828283
申请日：2007-07-25
申请人： Joseph A. Yedinak , Richard L. Woodin , Christopher Lawrence Rexer , Praveen Muraleedharan Shenoy , Kwanghoon Oh , Chongman Yun
发明人： Joseph A. Yedinak , Richard L. Woodin , Christopher Lawrence Rexer , Praveen Muraleedharan Shenoy , Kwanghoon Oh , Chongman Yun
IPC分类号： H01L27/02
CPC分类号： H01L29/872 , H01L27/0248 , H01L29/1608 , H01L29/8618 , H01L29/87
摘要： A wide bandgap device in parallel with a device having a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device.
摘要翻译：宽带隙器件与具有比宽带隙器件更低的雪崩击穿电压和更高的正向压降的器件并联。

10. 发明申请

US20090090966A1 HIGH DENSITY FET WITH INTEGRATED SCHOTTKY 有权
标题翻译：具有集成肖特基的高密度FET
公开(公告)号：US20090090966A1
公开(公告)日：2009-04-09
申请号：US12242633
申请日：2008-09-30
申请人： PAUL THORUP , Christopher Lawrence Rexer
发明人： PAUL THORUP , Christopher Lawrence Rexer
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L29/66734 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/47 , H01L29/66727 , H01L29/7806
摘要： A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.
摘要翻译：半导体结构包括单片集成沟槽FET和肖特基二极管。半导体结构还包括延伸到半导体区域中的多个沟槽。在每个沟槽中设置一叠栅极和屏蔽电极。主体区域在相邻沟槽之间的半导体区域上延伸，源区域在每个主体区域上延伸。具有锥形边缘的凹槽在两个相邻沟槽的每两个相邻的沟槽之间延伸穿过本体区域的两个相邻沟槽的上角，并终止在身体区域下方的半导体区域中。互连层延伸到每个凹部中以电接触源区域和主体区域的锥形侧壁，并且沿着每个凹部的底部接触半导体区域以在它们之间形成肖特基接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式