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1. 发明授权

US08008136B2 Fully silicided gate structure for FinFET devices 有权
标题翻译： FinFET器件的全硅化栅极结构
公开(公告)号：US08008136B2
公开(公告)日：2011-08-30
申请号：US11379435
申请日：2006-04-20
申请人： Ming-Ren Lin , Witold P. Maszara , Haihong Wang , Bin Yu
发明人： Ming-Ren Lin , Witold P. Maszara , Haihong Wang , Bin Yu
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7842
摘要： A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.
摘要翻译：一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物，在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

2. 发明授权

US08502283B2 Strained fully depleted silicon on insulator semiconductor device 有权
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件
公开(公告)号：US08502283B2
公开(公告)日：2013-08-06
申请号：US11926655
申请日：2007-10-29
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

3. 发明授权

US07306997B2 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor 失效
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件及其制造方法
公开(公告)号：US07306997B2
公开(公告)日：2007-12-11
申请号：US10986399
申请日：2004-11-10
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

4. 发明授权

US06238960B1 Fast MOSFET with low-doped source/drain 有权
标题翻译：具有低掺杂源极/漏极的快速MOSFET
公开(公告)号：US06238960B1
公开(公告)日：2001-05-29
申请号：US09483400
申请日：2000-01-14
申请人： Witold P. Maszara , Srinath Krishnan , Ming-Ren Lin
发明人： Witold P. Maszara , Srinath Krishnan , Ming-Ren Lin
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/6659 , H01L29/7833 , H01L29/78612 , H01L29/78621 , H01L29/78654
摘要： A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.
摘要翻译：形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124）氧化物（122）。随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一区域（60）和在其间具有沟道区（58）的第二区域（68）。方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域（60）和第二区域（68）中的源极区域（70）。源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

5. 发明授权

US06060364A Fast Mosfet with low-doped source/drain 有权
标题翻译：具有低掺杂源/漏极的快速Mosfet
公开(公告)号：US06060364A
公开(公告)日：2000-05-09
申请号：US260880
申请日：1999-03-02
申请人： Witold P. Maszara , Srinath Krishnan , Ming-Ren Lin
发明人： Witold P. Maszara , Srinath Krishnan , Ming-Ren Lin
IPC分类号： H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/6659 , H01L29/7833 , H01L29/78612 , H01L29/78621 , H01L29/78654
摘要： A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.
摘要翻译：形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124）氧化物（122）。随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一区域（60）和在其间具有沟道区（58）的第二区域（68）。方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域（60）和第二区域（68）中的源极区域（70）。源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

6. 发明授权

US06486038B1 Method for and device having STI using partial etch trench bottom liner 有权
标题翻译：使用局部蚀刻槽底衬的STI和器件的方法
公开(公告)号：US06486038B1
公开(公告)日：2002-11-26
申请号：US09804360
申请日：2001-03-12
申请人： Witold P. Maszara , Ming-Ren Lin , Qi Xiang
发明人： Witold P. Maszara , Ming-Ren Lin , Qi Xiang
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76283
摘要： A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of (a) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; (b) etching the silicon active layer to form an isolation trench wherein an unetched silicon layer at bottom of the isolation trench remains; (c) oxidizing the layer of silicon at the bottom of the isolation trench to a degree sufficient to oxidize through the layer of silicon at the bottom to the dielectric isolation layer; and (d) filling the isolation trench with a trench isolation material to form a shallow trench isolation structure.
摘要翻译：一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：（a）提供具有硅有源层，介电隔离层和硅衬底的绝缘体上硅半导体晶片，其中在介电隔离层上形成硅有源层，并在硅衬底上形成电介质隔离层; （b）蚀刻硅有源层以形成隔离沟槽，其中保留隔离沟槽底部的未蚀刻硅层; （c）将隔离沟槽的底部的硅层氧化至足以通过底部的硅层氧化成电介质隔离层的程度; 和（d）用沟槽隔离材料填充隔离沟槽以形成浅沟槽隔离结构。

7. 发明授权

US06204138B1 Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects 有权
标题翻译：制造MOSFET器件结构的方法，其有助于缓解结电容和浮体效应
公开(公告)号：US06204138B1
公开(公告)日：2001-03-20
申请号：US09260821
申请日：1999-03-02
申请人： Srinath Krishnan , Witold P. Maszara , Ming-Ren Lin
发明人： Srinath Krishnan , Witold P. Maszara , Ming-Ren Lin
IPC分类号： H01L21336
CPC分类号： H01L29/78612 , H01L29/78621
摘要： A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.
摘要翻译：提供了一种形成MOSFET器件的方法。形成第一轻掺杂区域，第一轻掺杂区域包括器件的LDD延伸区域。第二非常轻掺杂的区域至少部分地形成在第一轻掺杂区域的下方，第二非常轻掺杂的区域具有小于第一轻掺杂区域的掺杂剂浓度，并且第二极轻掺杂区域以较高能量水平比第一轻掺杂区域。

8. 发明授权

US06586808B1 Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric 有权
标题翻译：具有多功能栅极电极和多段栅极电介质的半导体器件
公开(公告)号：US06586808B1
公开(公告)日：2003-07-01
申请号：US10163696
申请日：2002-06-06
申请人： Qi Xiang , Witold P. Maszara , HaiHong Wang
发明人： Qi Xiang , Witold P. Maszara , HaiHong Wang
IPC分类号： H01L31119
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/28114 , H01L21/28167 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/42368 , H01L29/42376 , H01L29/42384 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66553 , H01L29/6659
摘要： A MOSFET and methods of fabrication. The MOSFET includes a gate having a center gate electrode portion being spaced from the layer of semiconductor material by a center gate dielectric. The gate also includes a lateral gate electrode portion adjacent each sidewall of the center gate electrode portion. The lateral gate electrode portions are each spaced from the layer of semiconductor material by a lateral gate dielectric portion.
摘要翻译：一种MOSFET及其制造方法。 MOSFET包括具有通过中心栅极电介质与半导体材料层间隔开的中心栅电极部分的栅极。栅极还包括与中心栅电极部分的每个侧壁相邻的横向栅极电极部分。横向栅极电极部分通过横向栅极电介质部分与半导体材料层间隔开。

9. 发明授权

US06630720B1 Asymmetric semiconductor device having dual work function gate and method of fabrication 有权
标题翻译：具有双功函数栅极和制造方法的非对称半导体器件
公开(公告)号：US06630720B1
公开(公告)日：2003-10-07
申请号：US10036210
申请日：2001-12-26
申请人： Witold P. Maszara , HaiHong Wang , Qi Xiang
发明人： Witold P. Maszara , HaiHong Wang , Qi Xiang
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L21/0337 , H01L21/84 , H01L27/1203
摘要： An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain.
摘要翻译：非对称半导体器件和制造一对不对称器件的方法。半导体器件包括具有源极和漏极的半导体材料层，以及设置在半导体材料层上以限定插入在源极和漏极之间的沟道的双功函数栅极。

10. 发明申请

US20140070322A1 METHODS OF FORMING DIFFERENT FINFET DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND INTEGRATED CIRCUIT PRODUCTS CONTAINING SUCH DEVICES 有权
标题翻译：形成具有不同阈值电压的不同FINFET器件的方法和包含这些器件的集成电路产品
公开(公告)号：US20140070322A1
公开(公告)日：2014-03-13
申请号：US13613508
申请日：2012-09-13
申请人： Ajey P. Jacob , Witold P. Maszara , Kerem Akarvardar
发明人： Ajey P. Jacob , Witold P. Maszara , Kerem Akarvardar
IPC分类号： H01L21/20 , H01L27/088
CPC分类号： H01L21/823431 , H01L21/8252 , H01L21/8258 , H01L27/0886 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中和上方形成用于第一FinFET器件的第一鳍片，其中第一鳍片由不同于半导体衬底的材料的第一半导体材料组成，并且在形成第一鳍片之后形成在所述半导体衬底中以及所述半导体衬底上形成的第二FinFET器件的第二鳍片，其中所述第二鳍片由不同于所述半导体衬底的材料并且不同于所述第一半导体材料的第二半导体材料构成。

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