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    • 2. 发明授权
    • Time-interleaved band-pass delta-sigma modulator
    • 时间交织的带通Δ-Σ调制器
    • US07145491B2
    • 2006-12-05
    • US10522373
    • 2002-08-29
    • Gun-Hee HanMin-Ho KwonJung-Yoon Lee
    • Gun-Hee HanMin-Ho KwonJung-Yoon Lee
    • H03M1/00
    • H03M3/47H03M3/402H03M3/454
    • A time-interleaved bandpass delta-sigma modulator is developed which includes a first adder and a second adder and a comparator. An input signal is transmitted to the first adder according to the clock frequency of each channel block, and an n channel block output un of the first adder is transmitted to the first adder and the second adder of an n+2 channel block, and an n block output vn of the second adder is transmitted to the second adder of an n+2 block, and an output yn that passes through an n block comparator is transmitted to the first adder and the second adder of an n+2 block. Therefore, a modulator sequentially receives output from the comparator of each block for generating the final output y.
    • 开发了一种时间交织的带通Δ-Σ调制器,其包括第一加法器和第二加法器以及比较器。 根据每个通道块的时钟频率将输入信号发送到第一加法器,并且第一加法器的n个通道块输出u N n被发送到第一加法器,第二加法器 n + 2个通道块和第n个加法器的n个块输出端子n n n被发送到n + 2个块的第二加法器,并且输出y n n 通过n块比较器被传送到第n + 2块的第一加法器和第二加法器。 因此,调制器顺序地从每个块的比较器接收用于产生最终输出y的输出。
    • 3. 发明申请
    • Time-interleaved band-pass delta-sigma modulator
    • 时间交织的带通Δ-Σ调制器
    • US20050231407A1
    • 2005-10-20
    • US10522373
    • 2002-08-29
    • Gun-Hee HanMin-Ho KwonJung-Yoon Lee
    • Gun-Hee HanMin-Ho KwonJung-Yoon Lee
    • H03M3/00H03M1/00
    • H03M3/47H03M3/402H03M3/454
    • A time-interleaved bandpass delta-sigma modulator is developed which includes a first adder and a second adder and a comparator. An input signal is transmitted to the first adder according to the clock frequency of each channel block, and an n channel block output un of the first adder is transmitted to the first adder and the second adder of an n+2 channel block, and an n block output vn of the second adder is transmitted to the second adder of an n+2 block, and an output yn that passes through an n block comparator is transmitted to the first adder and the second adder of an n+2 block. Therefore, a modulator sequentially receives output from the comparator of each block for generating the final output y.
    • 开发了一种时间交织的带通Δ-Σ调制器,其包括第一加法器和第二加法器以及比较器。 根据每个通道块的时钟频率将输入信号发送到第一加法器,并且第一加法器的n个通道块输出u N n被发送到第一加法器,第二加法器 n + 2个通道块和第n个加法器的n个块输出端子n n n被发送到n + 2个块的第二加法器,并且输出y n n 通过n块比较器被传送到第n + 2块的第一加法器和第二加法器。 因此,调制器顺序地从每个块的比较器接收用于产生最终输出y的输出。