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    • 3. 发明授权
    • Analog to digital converters, image sensor systems, and methods of operating the same
    • 模数转换器,图像传感器系统及其操作方法
    • US08810676B2
    • 2014-08-19
    • US13270968
    • 2011-10-11
    • Seung-Hyun LimKwi-Sung YooKyoung-Min KohYu-Jin ParkChi-Ho HwangYong Lim
    • Seung-Hyun LimKwi-Sung YooKyoung-Min KohYu-Jin ParkChi-Ho HwangYong Lim
    • H04N5/228
    • H03M1/144H03M1/56H04N5/378
    • An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.
    • 模数转换器(ADC)可以包括多输入比较单元,其被配置为比较来自图像传感器的像素电压,包括在粗略操作模式期间修改的阶梯电压的比较电压和包括斜坡电压的斜坡电压 在精细操作模式下彼此修改,以提供指示与斜坡电压组合的比较电压是否大于或小于像素电压的比较结果信号。 选择控制信号生成单元可以接收比较结果信号和模式控制信号,以指示粗略或精细模式,以提供允许修改粗略模式中的比较电压并且保持比较电压恒定的选择控制信号 精细模式。 参考电压选择单元可以接收选择控制信号以控制比较电压的修改。
    • 4. 发明申请
    • PASSIVE MATRIX-ADDRESSABLE MEMORY APPARATUS
    • 被动矩阵可寻址存储器
    • US20100002489A1
    • 2010-01-07
    • US12495133
    • 2009-06-30
    • Hee-Chul LeeWoo-Young KimChi-Ho HwangYong-Soo LeeSang-Youl KimDu-Youn Ka
    • Hee-Chul LeeWoo-Young KimChi-Ho HwangYong-Soo LeeSang-Youl KimDu-Youn Ka
    • G11C11/22G11C11/00
    • G11C11/22
    • Disclosed is a passive matrix-addressable memory apparatus. The passive matrix-addressable memory apparatus comprises: a plurality of first electrode lines horizontally arranged with respect to each other; a plurality of second electrode lines disposed orthogonal to the plurality of first electrode lines to be horizontally arranged with respect to each other; a memory unit formed between the plurality of first electrode lines and the plurality of second electrode lines, and containing an electrically polarizable material exhibiting hysteresis; and a switch unit. The switch unit comprises: first electrodes of a cantilever structure respectively formed between the memory unit and the plurality of first electrode lines to be electrically connected to the plurality of first electrode lines; and second electrodes electrically connected to the memory unit to be spaced apart from the first electrodes to face the first electrodes.
    • 公开了一种无源矩阵寻址存储装置。 无源矩阵寻址存储装置包括:相对于彼此水平布置的多个第一电极线; 与所述多个第一电极线正交配置的多个第二电极线相对于彼此水平布置; 形成在所述多个第一电极线和所述多个第二电极线之间的存储单元,并且包含具有滞后性的电极化材料; 和开关单元。 开关单元包括:分别形成在存储单元和多个第一电极线之间的悬臂结构的第一电极,以电连接到多个第一电极线; 以及与所述存储单元电连接以与所述第一电极间隔开以面向所述第一电极的第二电极。
    • 5. 发明授权
    • Passive matrix-addressable memory apparatus
    • 无源矩阵寻址存储器
    • US07983066B2
    • 2011-07-19
    • US12495133
    • 2009-06-30
    • Hee-Chul LeeWoo-Young KimChi-Ho HwangYong-Soo LeeSang-Youl KimDu-Youn Ka
    • Hee-Chul LeeWoo-Young KimChi-Ho HwangYong-Soo LeeSang-Youl KimDu-Youn Ka
    • G11C11/22
    • G11C11/22
    • Disclosed is a passive matrix-addressable memory apparatus. The passive matrix-addressable memory apparatus comprises: a plurality of first electrode lines horizontally arranged with respect to each other; a plurality of second electrode lines disposed orthogonal to the plurality of first electrode lines to be horizontally arranged with respect to each other; a memory unit formed between the plurality of first electrode lines and the plurality of second electrode lines, and containing an electrically polarizable material exhibiting hysteresis; and a switch unit. The switch unit comprises: first electrodes of a cantilever structure respectively formed between the memory unit and the plurality of first electrode lines to be electrically connected to the plurality of first electrode lines; and second electrodes electrically connected to the memory unit to be spaced apart from the first electrodes to face the first electrodes.
    • 公开了一种无源矩阵寻址存储装置。 无源矩阵寻址存储装置包括:相对于彼此水平布置的多个第一电极线; 与所述多个第一电极线正交配置的多个第二电极线相对于彼此水平布置; 形成在所述多个第一电极线和所述多个第二电极线之间的存储单元,并且包含具有滞后性的电极化材料; 和开关单元。 开关单元包括:分别形成在存储单元和多个第一电极线之间的悬臂结构的第一电极,以电连接到多个第一电极线; 以及与所述存储单元电连接以与所述第一电极间隔开以面向所述第一电极的第二电极。