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1. 发明授权

US07300852B2 Method for manufacturing capacitor of semiconductor element 失效
标题翻译：制造半导体元件电容器的方法
公开(公告)号：US07300852B2
公开(公告)日：2007-11-27
申请号：US11089122
申请日：2005-03-24
申请人： Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Su Jin Chae , Young Dae Kim
发明人： Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Su Jin Chae , Young Dae Kim
IPC分类号： H01L21/20
CPC分类号： H01L21/02312 , H01L21/02178 , H01L21/02181 , H01L21/022 , H01L21/3144 , H01L28/60
摘要： A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.
摘要翻译：一种制造半导体元件的电容器的方法，包括：在半导体衬底上形成电容器的底部电极; 在底电极的上表面进行快速热硝化（RTN）; 对所获得的在氮化物气氛下的炉中具有底部电极的结构进行热处理以消除由RTN产生的应力; 在硝化的底部电极上形成Al 2 O 3 N 3和HfO 2 N 2电介质膜; 以及在Al 2 O 3和HfO 2 N 2电介质膜上形成电容器的平板电极。在底电极表面进行RTN之后进行热处理，从而可以减轻由RTN产生的应力，从而使电容器获得高电容，降低漏电流。

2. 发明申请

US20070264770A1 CAPACITOR FORMING METHOD 审中-公开
标题翻译：电容成型方法
公开(公告)号：US20070264770A1
公开(公告)日：2007-11-15
申请号：US11618796
申请日：2006-12-30
申请人： Keum Bum Lee , Hai Won Kim , Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Dong Su Park
发明人： Keum Bum Lee , Hai Won Kim , Ho Jin Cho , Jun Soo Chang , Eun A. Lee , Dong Su Park
IPC分类号： H01L21/8242 , H01L29/92
CPC分类号： H01L21/3141 , H01L21/02178 , H01L21/02189 , H01L21/022 , H01L21/0228 , H01L21/0234 , H01L27/10852 , H01L28/91
摘要： A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.
摘要翻译：形成电容器的方法包括在半导体衬底上形成凹模。存储节点形成在凹模上。包含氧化锆（ZrO 2）层的电介质层在第一温度下沉积在存储节点上。在包括自由基的气氛中，在高于第一温度的第二温度下进行介电层上的自由基堆积处理，以诱导电介质层的结晶。在该电介质层上形成一个平板节点。

3. 发明申请

US20080070398A1 Method For Fabricating Semiconductor Device Having Metal Fuse 审中-公开
标题翻译：制造具有金属保险丝的半导体器件的方法
公开(公告)号：US20080070398A1
公开(公告)日：2008-03-20
申请号：US11758512
申请日：2007-06-05
申请人： Dong Su Park , Ho Jin Cho , Keum Bum Lee , Su Jin Chae , Cheol-Hwan Park
发明人： Dong Su Park , Ho Jin Cho , Keum Bum Lee , Su Jin Chae , Cheol-Hwan Park
IPC分类号： H01L23/525
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection. The method further includes forming an inter-metal dielectric layer on the first metal interconnection and the fuse, forming a second metal interconnection on the inter-metal dielectric layer, forming a passivation layer on the second metal interconnection, and forming a fuse box in the passivation layer.
摘要翻译：这里公开了一种制造具有金属保险丝的半导体器件的方法。该方法包括在半导体衬底上形成平板电极，在平板电极上形成层间绝缘层，从底部依次形成含有硅或铝的阻挡金属层，第一金属层和含有硅或铝的抗反射层，顶层在层间绝缘层上。该方法还包括图案化抗反射层，第一金属层和阻挡金属层以形成第一金属互连。该方法还包括形成具有与第一金属互连相同的材料和结构的熔丝，同时形成第一金属互连。该方法还包括在第一金属互连和熔丝上形成金属间电介质层，在金属间绝缘层上形成第二金属互连，在第二金属互连上形成钝化层，并在第钝化层。

4. 发明授权

US06955974B2 Method for forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US06955974B2
公开(公告)日：2005-10-18
申请号：US10877714
申请日：2004-06-25
申请人： Tae Hyeok Lee , Cheol Hwan Park , Dong Su Park , Ho Jin Cho , Eun A Lee
发明人： Tae Hyeok Lee , Cheol Hwan Park , Dong Su Park , Ho Jin Cho , Eun A Lee
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242
CPC分类号： H01L21/76224 , H01L27/10894
摘要： A method for forming an isolation layer of a semiconductor device, which comprises the steps of: a) sequentially forming a pad oxide layer and a pad nitride layer on a silicon substrate; b) etching the pad nitride layer, the pad oxide layer, and the silicon substrate, thereby forming a trench; c) thermal-oxidizing the resultant substrate to form a sidewall oxide layer on a surface of the trench; d) nitrifying the sidewall oxide layer through the use of NH3 annealing; e) depositing a liner aluminum nitride layer on an entire surface of the silicon substrate inclusive of the nitrated sidewall oxide layer; f) depositing a buried oxide layer on the liner aluminum nitride layer to fill the trench; g) performing a chemical mechanical polishing process with respect to the buried oxide layer; and h) eliminating the pad nitride layer.
摘要翻译：一种用于形成半导体器件的隔离层的方法，包括以下步骤：a）在硅衬底上依次形成焊盘氧化物层和衬垫氮化物层; b）蚀刻衬垫氮化物层，衬垫氧化物层和硅衬底，从而形成沟槽; c）热氧化所得衬底以在沟槽的表面上形成侧壁氧化物层; d）通过使用NH 3退火对侧壁氧化物层进行硝化; e）在包括所述硝化侧壁氧化物层的所述硅衬底的整个表面上沉积衬里氮化铝层; f）在衬里氮化铝层上沉积掩埋氧化物层以填充沟槽; g）对所述掩埋氧化物层进行化学机械抛光工艺; 以及h）消除所述衬垫氮化物层。

5. 发明授权

US08470668B2 Method for forming pillar type capacitor of semiconductor device 有权
标题翻译：半导体器件柱状电容器形成方法
公开(公告)号：US08470668B2
公开(公告)日：2013-06-25
申请号：US12979926
申请日：2010-12-28
申请人： Ho Jin Cho , Cheol Hwan Park , Dong Kyun Lee
发明人： Ho Jin Cho , Cheol Hwan Park , Dong Kyun Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10852 , H01L27/10855 , H01L28/90
摘要： An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.
摘要翻译：本发明的实施例包括柱形电容器，其中柱形成在存储节点接触件的上部上。底部电极形成在支柱的侧壁上，电介质膜形成在支柱和底部电极之上。然后在电介质膜的上部上形成顶部电极。

6. 发明授权

US07985645B2 Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same 有权
标题翻译：具有高方位圆柱形电容器的半导体器件及其制造方法
公开(公告)号：US07985645B2
公开(公告)日：2011-07-26
申请号：US12649610
申请日：2009-12-30
申请人： Cheol Hwan Park , Ho Jin Cho , Dong Kyun Lee
发明人： Cheol Hwan Park , Ho Jin Cho , Dong Kyun Lee
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L27/10894
摘要： A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
摘要翻译：提出了具有高方位圆柱形电容器的半导体器件及其制造方法。高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。存储节点氧化物位于半导体衬底上的周边区域中。导电层涂覆保护环孔。在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。覆盖氧化物部分地填充导电层的一部分。间隙填充膜填充在导电层的其余部分。

7. 发明授权

US06355521B1 Method of manufacturing a capacitor in a semiconductor device 失效
标题翻译：在半导体器件中制造电容器的方法
公开(公告)号：US06355521B1
公开(公告)日：2002-03-12
申请号：US09659509
申请日：2000-09-11
申请人： Ho Jin Cho
发明人： Ho Jin Cho
IPC分类号： H01L21336
CPC分类号： H01L28/60 , H01L21/31604 , H01L28/91
摘要： The present invention discloses a method of manufacturing a capacitor in a semiconductor device which is directed to solve the problem of reduction of capacitance occurring when manufacturing a capacitor of a MIS structure using poly-silicon as an underlying electrode and metal as an upper electrode in a capacitor using Ta2O5 as a dielectric film. In order to solve the problem, the present invention forms an underlying electrode using metal having a good oxide-resistant such as TiSiN. Thus, the present invention could not only lower the thickness of the effective oxide film of Ta2O5 when depositing Ta2O5 or performing a thermal process for crystallization but also prevent increase of a leak current due to oxidization of the underlying electrode and the diffusion prevention film, thus securing the capacitance of the capacitor and improving the electric characteristic of the capacitor.
摘要翻译：本发明公开了一种在半导体器件中制造电容器的方法，该方法旨在解决当制造使用多晶硅作为底层电极的MIS结构的电容器和在金属作为上部电极的金属制造时发生的电容减小的问题电容器采用Ta2O5作为电介质膜。为了解决这个问题，本发明利用TiSiN等具有良好的耐氧化性的金属形成下层电极。因此，本发明不仅可以降低Ta2O5的有效氧化膜的厚度，还可以防止由于底层电极和扩散防止膜的氧化引起的漏电流的增加，确保电容器的电容并改善电容器的电气特性。

8. 发明授权

US06306666B1 Method for fabricating ferroelectric memory device 失效
标题翻译：铁电存储器件的制造方法
公开(公告)号：US06306666B1
公开(公告)日：2001-10-23
申请号：US09461844
申请日：1999-12-15
申请人： Ho Jin Cho
发明人： Ho Jin Cho
IPC分类号： H01G706
CPC分类号： H01L28/55 , H01L21/28568 , H01L21/31691 , H01L28/75
摘要： The present invention provides a method for fabricating a ferroelectric memory device capable of preventing formation of an oxide layer between a BST layer and a storage node electrode with using a general electrode that is easy to etch, as a storage node electrode. The method comprises the steps of: forming successively a barrier layer and a metal layer for storage node electrode on the intermetal insulating layer; forming a storage node electrode by patterning the metal layer for storage node electrode and the barrier layer to be contact with the contact plug; depositing a ferroelectric layer on the storage node electrode and the intermetal insulating layer at a temperature that the storage node electrode is not oxidized; crystallizing the ferroelectric layer; and forming a plate electrode on the ferroelectric layer, wherein the ferroelectric layer is deposited at temperature of 100˜400° C. according to the MOCVD method.
摘要翻译：本发明提供了一种制造铁电存储器件的方法，所述铁电存储器件能够防止在使用容易蚀刻的一般电极之间形成BST层和存储节点电极之间的氧化物层作为存储节点电极。该方法包括：步骤：在金属间绝缘层上连续形成用于存储节点电极的阻挡层和金属层; 通过图案化用于存储节点电极的金属层和阻挡层与接触插塞接触来形成存储节点电极; 在存储节点电极未被氧化的温度下，在存储节点电极和金属间绝缘层上沉积铁电层; 结晶铁电层; 并在铁电层上形成平板电极，其中根据MOCVD方法在100〜400℃的温度下沉积铁电体层。

9. 发明授权

US08476688B2 Semiconductor device and method for manufacturing the same,which prevents leaning of a storage node when forming a capacitor having a plurality of storage nodes of “L” or “+” shape support patterns 失效
标题翻译：半导体装置及其制造方法，当形成具有多个“L”或“+”形状的支撑图案的存储节点的电容器时，防止存储节点倾斜
公开(公告)号：US08476688B2
公开(公告)日：2013-07-02
申请号：US12244115
申请日：2008-10-02
申请人： Ho Jin Cho , Cheol Hwan Park , Jae Wook Seo , Jong Kuk Kim
发明人： Ho Jin Cho , Cheol Hwan Park , Jae Wook Seo , Jong Kuk Kim
IPC分类号： H01L31/113
CPC分类号： H01L28/91 , H01L27/10852
摘要： A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.
摘要翻译：当形成具有高电容的电容器时，防止存储节点倾斜的半导体器件包括形成在半导体衬底上的多个圆柱形存储节点; 以及当从顶部观察时，形成为以“L”或“+”的形式固定存储节点的支撑图案。具有“L”或“+”形式的支撑图案的这种半导体器件随后形成介电层并且防止电容器泄漏的板节点减小了存储节点上的应力。

10. 发明授权

US07871939B2 Method for manufacturing semiconductor device using a free radical assisted chemical vapor deposition nitrifying process 失效
标题翻译：使用自由基辅助化学气相沉积硝化工艺制造半导体器件的方法
公开(公告)号：US07871939B2
公开(公告)日：2011-01-18
申请号：US11966185
申请日：2007-12-28
申请人： Gyu Dong Cho , Ho Jin Cho , Hyun Jung Kim
发明人： Gyu Dong Cho , Ho Jin Cho , Hyun Jung Kim
IPC分类号： H01L21/31
CPC分类号： H01L29/66621 , H01L21/28061 , H01L21/28247 , H01L21/3143
摘要： A method for manufacturing a semiconductor device for use in avoiding unwanted oxidation along exposed surfaces and for use in relieving etching damage is presented. The method includes step of forming sequentially a gate insulation layer, a polysilicon layer, a barrier layer, a metallic layer and a hard mask layer over a semiconductor substrate. The method also includes a step of etching the hard mask layer, the metallic layer, the barrier layer, the polysilicon layer and the gate insulation layer to form a gate. The method also includes a nitrifying step which uses a free radical is assisted chemical vapor deposition (RACVD) nitrifying process on surfaces of the layers forming the gate and a surface of the semiconductor substrate. The method also includes a step of subsequently performing a reoxidation process to the semiconductor substrate resultant that the RACVD nitrifying process is performed.
摘要翻译：本发明提供一种制造半导体器件的方法，该半导体器件用于避免暴露表面的不必要的氧化并用于缓解蚀刻损伤。该方法包括在半导体衬底上依次形成栅极绝缘层，多晶硅层，势垒层，金属层和硬掩模层的步骤。该方法还包括蚀刻硬掩模层，金属层，势垒层，多晶硅层和栅极绝缘层以形成栅极的步骤。该方法还包括在形成栅极和半导体衬底的表面的表面上使用自由基辅助化学气相沉积（RACVD）硝化过程的硝化步骤。该方法还包括随后对半导体衬底的再氧化过程产生RACVD硝化过程的步骤。

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