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1. 发明授权

US11784077B2 Wafer overlay marks, overlay measurement systems, and related methods 有权
公开(公告)号：US11784077B2
公开(公告)日：2023-10-10
申请号：US16719366
申请日：2019-12-18
申请人： Micron Technology, Inc.
发明人： Denzil S. Frost , Richard T. Housley , David S. Pratt , Trupti D. Gawai
IPC分类号： H01L23/544 , H01L21/68 , G06T7/00 , G06T7/73 , G03F7/00
CPC分类号： H01L21/681 , G06T7/0004 , G06T7/73 , H01L23/544 , G03F7/70633 , G06T2207/10056 , G06T2207/30148 , H01L2223/544 , H01L2223/54426 , H01L2223/54493
摘要： A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of an overlay mark with a direction in which a source emits light at the wafer and align other portions of the lines of the pattern to extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining contrasts of regions of the overlay mark and determining a location of the overlay mark. Overlay marks include a pattern defining an array of columns. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of a column and extending in a second different direction in a second region of the column.

2. 发明授权

US11251096B2 Wafer registration and overlay measurement systems and related methods 有权
公开(公告)号：US11251096B2
公开(公告)日：2022-02-15
申请号：US16122106
申请日：2018-09-05
申请人： Micron Technology, Inc.
发明人： Nikolay A. Mirin , Robert Dembi , Richard T. Housley , Xiaosong Zhang , Jonathan D. Harms , Stephen J. Kramer
IPC分类号： G03F7/20 , H01L21/68 , H01L21/66 , H01L23/544 , H01L21/302
摘要： A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.

3. 发明授权

US11520240B2 Wafer alignment markers, systems, and related methods 有权
公开(公告)号：US11520240B2
公开(公告)日：2022-12-06
申请号：US17314410
申请日：2021-05-07
申请人： Micron Technology, Inc.
发明人： Nikolay A. Mirin , Robert Dembi , Richard T. Housley , Xiaosong Zhang , Jonathan D. Harms , Stephen J. Kramer
IPC分类号： G03F7/20 , H01L21/68 , G01R33/07 , H01L23/544
摘要： A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

4. 发明申请

US20140301126A1 Memory Arrays and Methods of Forming Electrical Contacts 有权
标题翻译：记忆阵列和形成电触点的方法
公开(公告)号：US20140301126A1
公开(公告)日：2014-10-09
申请号：US14308584
申请日：2014-06-18
申请人： Micron Technology, Inc.
发明人： Richard T. Housley
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , H01L21/743 , H01L27/088 , H01L27/10891 , H01L27/10894 , H01L29/66666
摘要： Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays.
摘要翻译：一些实施例包括形成电触点的方法。可以形成一排半导体材料突起，其中半导体材料突起包含阵列的重复部件，并且该行的端子半导体突起包括接触位置。导电线可以沿着所述行，线绕着所述端子半导体突起的端部并分叉成沿半导体材料突起的相对侧分成两个分支。端子半导体突起的一些半导体材料可以用介电材料代替，然后可以将开口延伸到电介质材料中。可以在开口内形成电接触并且直接抵靠至少一个分支。一些实施例包括存储器阵列。

5. 发明申请

US20140045317A1 Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate 有权
标题翻译：形成记忆体阵列的方法，形成多个场效应晶体管的方法，形成源极/漏极区域的方法和隔离沟槽以及将一系列间距沟槽形成基板的方法
公开(公告)号：US20140045317A1
公开(公告)日：2014-02-13
申请号：US14053665
申请日：2013-10-15
申请人： Micron Technology, Inc.
发明人： Neal L. Davis , Richard T. Housley , Ranjan Khurana
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/3065 , H01L21/3086 , H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L27/105 , H01L27/1052
摘要： A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.
摘要翻译：将一系列间隔开的沟槽形成到衬底中的方法包括在衬底上形成多个间隔开的线。各向异性蚀刻的侧壁间隔物形成在间隔开的线的相对侧上。这些线的个体具有比在紧邻线之间的紧邻的间隔物之间的最小宽度的最大宽度。去除间隔的线以在间隔件之间形成一系列交替的第一和第二掩模开口。第一掩模开口位于间隔开的线的位置并且比第二掩模开口更宽。交替的第一和第二沟槽分别通过交替的第一和第二掩模开口同时蚀刻到衬底中，以形成比第二沟槽在衬底内更宽和更深的第一沟槽。公开了其他实现和实施例。

6. 发明申请

US20130228874A1 Memory Arrays and Methods of Forming Electrical Contacts 有权
标题翻译：记忆阵列和形成电触点的方法
公开(公告)号：US20130228874A1
公开(公告)日：2013-09-05
申请号：US13857855
申请日：2013-04-05
申请人： MICRON TECHNOLOGY, INC.
发明人： Richard T. Housley
IPC分类号： H01L27/088
CPC分类号： G11C5/06 , H01L21/743 , H01L27/088 , H01L27/10891 , H01L27/10894 , H01L29/66666
摘要： Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays.
摘要翻译：一些实施例包括形成电触点的方法。可以形成一排半导体材料突起，其中半导体材料突起包含阵列的重复部件，并且该行的端子半导体突起包括接触位置。导电线可以沿着所述行，线绕着所述端子半导体突起的端部并分叉成沿半导体材料突起的相对侧分成两个分支。端子半导体突起的一些半导体材料可以用介电材料代替，然后可以将开口延伸到电介质材料中。可以在开口内形成电接触并且直接抵靠至少一个分支。一些实施例包括存储器阵列。

7. 发明公开

US20240243072A1 Integrated Circuitry, Memory Circuitry Comprising Strings Of Memory Cells, And Methods Used In Forming Integrated Circuitry 审中-公开
公开(公告)号：US20240243072A1
公开(公告)日：2024-07-18
申请号：US18408194
申请日：2024-01-09
申请人： Micron Technology, Inc.
发明人： Kar Wui Thong , Harsh Narendrakumar Jain , Richard T. Housley , Manampurathu Sivaramapanicker Suresh Kumar
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/5446 , H10B43/27
摘要： A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. The stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. The scribe-line area comprises a horizontal area in which a registration mark or an alignment mark is being fabricated. Horizontally-spaced features of the registration mark or of the alignment mark are simultaneously formed in the first tiers and the second tiers in the horizontal area and in the individual die areas. The horizontally-spaced features in the horizontal area are grouped in sections that are horizontally-separated by gaps in at least one vertical cross-section where there are less, if any, such horizontally-spaced features than are in the sections. Horizontally-spaced vertical slots are formed through uppermost of the first and second tiers of the stack in the horizontal area of the registration mark or of the alignment mark. Through the horizontally-spaced vertical slots, the sacrificial material is replaced with metal material. After the replacing, the first and second tiers in the scribe-line areas are cut through to form individual die that individually comprise one of the individual die areas. Other embodiments, including structure, are disclosed.

8. 发明申请

US20210193493A1 WAFER OVERLAY MARKS, OVERLAY MEASUREMENT SYSTEMS, AND RELATED METHODS 有权
公开(公告)号：US20210193493A1
公开(公告)日：2021-06-24
申请号：US16719366
申请日：2019-12-18
申请人： Micron Technology, Inc.
发明人： Denzil S. Frost , Richard T. Housley , David S. Pratt , Trupti D. Gawai
IPC分类号： H01L21/68 , H01L23/544 , G06T7/00 , G06T7/73
摘要： A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of an overlay mark with a direction in which a source emits light at the wafer and align other portions of the lines of the pattern to extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining contrasts of regions of the overlay mark and determining a location of the overlay mark. Overlay marks include a pattern defining an array of columns. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of a column and extending in a second different direction in a second region of the column.

9. 发明授权

US10756022B2 Methods of alignment marking semiconductor wafers, and semiconductor packages having portions of alignment markings 有权
公开(公告)号：US10756022B2
公开(公告)日：2020-08-25
申请号：US16554118
申请日：2019-08-28
申请人： Micron Technology, Inc.
发明人： Richard T. Housley , Jianming Zhou
IPC分类号： H01L21/00 , H01L23/544 , H01L21/78
摘要： Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.

10. 发明授权

US09343114B2 Memory arrays and methods of forming electrical contacts 有权
标题翻译：存储器阵列和形成电触点的方法
公开(公告)号：US09343114B2
公开(公告)日：2016-05-17
申请号：US14308584
申请日：2014-06-18
申请人： Micron Technology, Inc.
发明人： Richard T. Housley
IPC分类号： H01L21/70 , G11C5/06 , H01L27/108 , H01L21/74 , H01L27/088 , H01L29/66
CPC分类号： G11C5/06 , H01L21/743 , H01L27/088 , H01L27/10891 , H01L27/10894 , H01L29/66666
摘要： Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays.
摘要翻译：一些实施例包括形成电触点的方法。可以形成一排半导体材料突起，其中半导体材料突起包含阵列的重复部件，并且该行的端子半导体突起包括接触位置。导电线可以沿着所述行，线绕着所述端子半导体突起的端部并分叉成沿半导体材料突起的相对侧分成两个分支。端子半导体突起的一些半导体材料可以用介电材料代替，然后可以将开口延伸到电介质材料中。可以在开口内形成电接触并且直接抵靠至少一个分支。一些实施例包括存储器阵列。

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