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1. 发明授权

EP3341937B1 FULLY DEPLETED SILICON ON INSULATOR FLASH MEMORY DESIGN 有权转让
公开(公告)号：EP3341937B1
公开(公告)日：2024-10-30
申请号：EP16854057.3
申请日：2016-09-14
IPC分类号： G11C8/08 , G11C16/08 , H10B43/27
CPC分类号： G11C7/065 , G11C8/08 , G11C16/10 , G11C16/28 , G11C2216/0420130101 , H01L28/00 , G11C16/14 , G11C16/08 , G11C16/26 , H10B43/27

2. 发明公开

EP4451820A1 SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 审中-公开
公开(公告)号：EP4451820A1
公开(公告)日：2024-10-23
申请号：EP24165724.6
申请日：2024-03-24
申请人： Samsung Electronics Co., Ltd.
发明人： LEE, Hyemi , KIM, Seungyoon , KIM, Heesuk , LEE, Sangjae , LEE, Jaehoon , LIM, Juyoung , CHUNG, Minkyu , CHUN, Sanghun , HAN, Jeehoon
IPC分类号： H10B43/10 , H10B43/27 , H10B43/50
CPC分类号： H10B43/10 , H10B43/27 , H10B43/50
摘要： A semiconductor device includes a plate layer, gate electrodes and interlayer insulating layers alternately stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and forming a first stack structure and a second stack structure on the first stack structure, a channel structure penetrating through the gate electrodes and extending in the first direction, and a contact plug extending in the first direction and electrically connected to one of the gate electrodes, wherein the second stack structure includes a first gate electrode on a lowermost portion, a first interlayer insulating layer on the first gate electrode, and a second interlayer insulating layer on the first interlayer insulating layer, and the first interlayer insulating layer has a first thickness, and the second interlayer insulating layer has a second thickness smaller than the first thickness.

3. 发明公开

EP4440277A1 THREE-DIMENSIONAL MEMORY AND MANUFACTURING METHOD THEREFOR, AND STORAGE SYSTEM 审中-实审
公开(公告)号：EP4440277A1
公开(公告)日：2024-10-02
申请号：EP21968477.6
申请日：2021-12-21
申请人： Yangtze Memory Technologies Co., Ltd.
发明人： LIU, Xiaoxin , XUE, Lei
IPC分类号： H10B43/40
CPC分类号： H10B43/27 , H10B43/35
摘要： The application provides a three-dimensional memory and the method for manufacturing the same, and a memory system. The memory comprises: a bottom select gate structure; a stack structure disposed on the bottom select gate structure, the stack structure including a channel layer extending in stack structure in the first direction of the thickness of the stack structure, the channel layer having a first conductive type impurity; a top select gate structure disposed on the stack structure, wherein at least one of the bottom select gate structure and the top select gate structure comprises a semiconductor structure extending in the first direction and connected with the channel layer and having a second conductive type impurity opposite to the first conductive type impurity. The memory provided in the present application can form a PN junction barrier capacitance in a conductive circuit connecting a channel layer by providing a semiconductor structure having an impurity of an opposite conductive type to the channel layer in a select gate structure. Therefore, the width of the space charge region in the capacitor above described can be modulated according to the requirements of the erasing, programming and read operation, and the turn-on speed of the channel layer can be controlled to optimize the turn-on/turn-off performance of the three-dimensional memory.

4. 发明公开

EP4436332A1 NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开
公开(公告)号：EP4436332A1
公开(公告)日：2024-09-25
申请号：EP24162357.8
申请日：2024-03-08
申请人： Samsung Electronics Co., Ltd.
发明人： PARK, Kyeonghoon , BAEK, Jaebok , YUN, Janggn , HAN, Jeehoon
IPC分类号： H10B43/27 , H10B43/10 , H10B43/40 , H10B43/50
CPC分类号： H10B43/27 , H10B43/10 , H10B43/40 , H10B43/50
摘要： A non-volatile memory device includes a peripheral circuit structure and a cell array structure on the peripheral circuit structure, where the cell array structure includes a base insulation layer, a common source line layer on the base insulation layer, a buffer insulation layer on the common source line layer, and a cell stack on the buffer insulation layer, where the cell stack includes a plurality of gate electrodes and a plurality of insulation layers, where the plurality of gate electrodes have a staircase shape, a plurality of gate contact plugs that extend into the cell stack, and a plurality of protection structures between the plurality of gate contact plugs and the base insulation layer.

5. 发明公开

EP4432807A1 INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME 审中-公开
公开(公告)号：EP4432807A1
公开(公告)日：2024-09-18
申请号：EP24157124.9
申请日：2024-02-12
申请人： Samsung Electronics Co., Ltd.
发明人： PARK, Kyeonghoon , KIM, Hyunho , BAEK, Jaebok , YUN, Janggn , HAN, Jeehoon
IPC分类号： H10B43/27 , H10B41/27
CPC分类号： H10B43/27 , H10B41/27
摘要： Provided is an integrated circuit device with increased electrical reliability by forming an ohmic junction between a contact structure and a wiring line by bypassing a common source line such that the common source line, to which a common source line driver is connected, is electrically connected to the contact structure through the wiring line.

6. 发明公开

EP4258843A3 SOURCE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME 审中-实审
公开(公告)号：EP4258843A3
公开(公告)日：2024-08-07
申请号：EP23193785.5
申请日：2018-03-01
申请人： Yangtze Memory Technologies Co., Ltd.
发明人： HU, Yushi , LU, Zhenyu , TAO, Qian , CHEN, Jun , YANG, Simon Shi-Ning , YANG, Steve Weiyi
IPC分类号： H10B43/27 , H10B43/40
CPC分类号： H10B43/40 , H10B43/27
摘要： Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.

7. 发明公开

EP4401526A1 NON-VOLATILE MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-实审
公开(公告)号：EP4401526A1
公开(公告)日：2024-07-17
申请号：EP23191023.3
申请日：2023-08-11
申请人： Samsung Electronics Co., Ltd.
发明人： LEE, Jung-Hwan , CHO, Hyunmin
IPC分类号： H10B43/27 , H10B41/27 , H10B41/10 , H10B43/10
CPC分类号： H10B43/27 , H10B43/10 , H10B41/27 , H10B41/10
摘要： A non-volatile memory device may include a channel structure including a first stacking structure (GS1), a second stacking structure (GS2), a first channel structure (CH1) penetrating the first stacking structure (GS1), and a second channel structure (CH2) penetrating the second stacking structure (GS2). The second channel structure (CH2) includes a first portion (P1) having a width that decreases or is maintained as the first portion (P1) extends toward a substrate (101), and a second portion (P2) having a width that increases as the second portion (P2) extends toward the substrate (101).

8. 发明公开

EP4395493A1 SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-实审
公开(公告)号：EP4395493A1
公开(公告)日：2024-07-03
申请号：EP23196723.3
申请日：2023-09-12
申请人： Samsung Electronics Co., Ltd.
发明人： LEE, Gil Sung , SUNG, Suk Kang
IPC分类号： H10B43/10 , H10B43/27 , H10B43/50 , H10B43/35
CPC分类号： H10B43/10 , H10B43/27 , H10B43/50 , H10B43/35
摘要： A semiconductor memory device may include a cell substrate, a mold structure including gate electrodes stacked on the cell substrate, a channel structures (CH1, CH2, CH3) penetrating the mold structure; and a first cutting structure (SLC) cutting some of the gate electrodes. The first cutting structure may include a first portion (SLC1) having a line shape extending in a first direction and a second portion (SLC2) having a line shape extending in a second direction. The first portion and the second portion may be alternately connected to form a zigzag shape. The first cutting structure may include a first side wall and a second side wall opposing the first side wall. A first point of the first side wall connected from the second portion to the first portion and a second point of the second side wall connected from the first portion to the second portion may be in corresponding channel structures among the channel structures.

9. 发明公开

EP4391761A1 VERTICAL NAND FLASH MEMORY DEVICE 审中-实审
公开(公告)号：EP4391761A1
公开(公告)日：2024-06-26
申请号：EP23187580.8
申请日：2023-07-25
申请人： Samsung Electronics Co., Ltd.
发明人： KIM, Kyunghun , KIM, Sunho , KIM, Seyun , KIM, Hyungyung , YANG, Seungyeul , YON, Gukhyon , LEE, Minhyun , CHOI, Seokhoon , HEO, Hoseok
IPC分类号： H10B43/27 , H10B43/30 , H01L29/423 , H01L29/792
CPC分类号： H10B43/30 , H10B43/27 , H01L29/42324 , H01L29/7926
摘要： A vertical NAND flash memory device may include a plurality of cell arrays (110). Each of the plurality of cell arrays may include a channel layer (129), a charge trap layer (125) on the channel layer, and a plurality of gate electrodes (121) on the charge trap layer. The charge trap layer may include silicon oxynitride comprising a metal. The metal may include at least one of Ga or In.

10. 发明公开

EP4383342A3 SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-实审
公开(公告)号：EP4383342A3
公开(公告)日：2024-06-26
申请号：EP23213815.6
申请日：2023-12-01
申请人： Samsung Electronics Co., Ltd.
发明人： YUN, Kangoh , LEE, Sohyun , LEE, Dongjin , LIM, Junhee
IPC分类号： H01L29/08 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/40 , H01L21/8234
CPC分类号： H10B43/27 , H10B43/40 , H10B43/10 , H10B41/27 , H10B41/40 , H10B41/10 , H01L29/0847 , H01L21/823418
摘要： A semiconductor device includes a substrate including an active region including a central active region extending in a first direction and first to fourth extended active regions extending from an edge of the central active region in a second direction perpendicular to the first direction, and a device isolation layer defining the active region; and first to fourth gate structures on the active region and spaced apart from one another, wherein the central active region, the first to fourth extended active regions, and the first to fourth gate structures constitute first to fourth pass transistors, the first to fourth pass transistors share one drain region on the central active region, and the active region has an H shape in a plan view.

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