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1. 发明授权

US06774467B2 Semiconductor device and process of production of same 有权
标题翻译：半导体器件及其生产工艺相同
公开(公告)号：US06774467B2
公开(公告)日：2004-08-10
申请号：US09812276
申请日：2001-03-20
申请人： Michio Horiuchi , Takashi Kurihara , Tomio Nagaoka , Masao Aoki , Shigeru Mizuno
发明人： Michio Horiuchi , Takashi Kurihara , Tomio Nagaoka , Masao Aoki , Shigeru Mizuno
IPC分类号： H01L23495
CPC分类号： H01L24/81 , H01L21/561 , H01L21/563 , H01L23/24 , H01L23/3107 , H01L23/3128 , H01L23/49816 , H01L23/4985 , H01L24/29 , H01L24/97 , H01L25/105 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13339 , H01L2224/13347 , H01L2224/16225 , H01L2224/16237 , H01L2224/29111 , H01L2224/2929 , H01L2224/73203 , H01L2224/81801 , H01L2224/83192 , H01L2224/83856 , H01L2224/97 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/12042 , H01L2924/15153 , H01L2924/15174 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/15747 , H01L2924/1579 , H01L2924/18161 , H01L2924/19041 , H01L2924/3511 , H01L2224/81 , H01L2924/01083 , H01L2924/00 , H01L2924/00014 , H01L2924/0665
摘要： Thin semiconductor device, especially a thin package, which reduces and achieves uniform mounting height, not requiring mounting of individual chips, improves manufacturing yield, without being affected by variation in chip thickness, enables testing alltogether, and process for producing same, the semiconductor mounted with back surface exposed upward, on top of an insulating substrate having throughholes in thickness direction, the area around semiconductor side surfaces being sealed by a resin layer, metal interconnections on the bottom surface of the substrate define bottom portions of throughholes of the substrate, a solder resist layer having throughholes in the thickness direction covers the bottom surface of metal interconnections and substrate, terminals extending downward from the active surface of the semiconductor are inserted into throughholes of the substrate, conductive filler fills gaps between the terminals and the throughholes of the substrate, and connection terminal and interconnections are electrically connected.
摘要翻译：薄型半导体器件，特别是薄封装，其减少并实现均匀的安装高度，而不需要安装单个芯片，提高了制造成品率，而不受芯片厚度变化的影响，能够进行全面测试，以及制造工艺，半导体安装背面向上露出，在厚度方向上具有通孔的绝缘基板的顶部，半导体侧面的周围的区域被树脂层密封，在基板的底面上的金属互连限定了基板的通孔的底部，在厚度方向上具有通孔的阻焊层覆盖金属互连和基板的底面，从半导体的有源表面向下延伸的端子插入到基板的通孔中，导电填料填充端子之间的间隙和基板的通孔，连接终端并且互连电连接。

2. 发明授权

US06849945B2 Multi-layered semiconductor device and method for producing the same 失效
标题翻译：多层半导体器件及其制造方法
公开(公告)号：US06849945B2
公开(公告)日：2005-02-01
申请号：US09881005
申请日：2001-06-14
申请人： Michio Horiuchi , Takashi Kurihara , Shigeru Mizuno
发明人： Michio Horiuchi , Takashi Kurihara , Shigeru Mizuno
IPC分类号： H01L23/12 , H01L23/498 , H01L23/52 , H01L23/538 , H01L25/10 , H01L25/11 , H01L25/18 , H01L23/48
CPC分类号： H01L23/49816 , H01L23/5385 , H01L24/50 , H01L25/105 , H01L2225/1035 , H01L2225/1058 , H01L2924/07802 , H01L2924/00
摘要： To minimize a size of a semiconductor device and reduce a thickness thereof as well as improve the yield and lower the production cost in the production of a semiconductor package, a multi-layered semiconductor device is provided, wherein a film-like semiconductor package (10) incorporating therein a semiconductor chip (12) is disposed in a package accommodation opening (11a) of a circuit pattern layer to form a circuit board. A plurality of such circuit boards are layered together to electrically connect circuit patterns (13) of the circuit boards with each other via a low melting point metal (14) or lead beam bonding (13b).
摘要翻译：为了最小化半导体器件的尺寸并减小其厚度，并且提高了半导体封装的制造中的产量并降低了生产成本，提供了一种多层半导体器件，其中膜状半导体封装（10 ）设置在电路图案层的封装容纳开口（11a）中以形成电路板。多个这样的电路板层叠在一起，通过低熔点金属（14）或引线束接合（13b）将电路板的电路图案（13）彼此电连接。

3. 发明授权

US06518672B2 Multi-layer wiring board substrate and semiconductor device using the multi-layer wiring substrate 有权
标题翻译：多层布线基板和使用多层布线基板的半导体器件
公开(公告)号：US06518672B2
公开(公告)日：2003-02-11
申请号：US09880978
申请日：2001-06-14
申请人： Takashi Kurihara , Michio Horiuchi , Shigeru Mizuno , Yuka Tamadate
发明人： Takashi Kurihara , Michio Horiuchi , Shigeru Mizuno , Yuka Tamadate
IPC分类号： H01L2348
CPC分类号： H05K3/363 , H01L23/49805 , H01L23/4985 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06551 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H05K1/144 , H05K2201/0397 , H05K2201/10681
摘要： A multi-layer wiring substrate comprises: a plurality of wiring substrates, each of the substrates comprising a plate or sheet-like insulating layer and a wiring layer formed on only one of surfaces of the insulating layer; the plurality of wiring substrates being laminated in such a manner that the insulating layer and wiring layer are alternately arranged; at least a pair of said wiring layers arranged on respective surfaces of the insulating layer being electrically connected with each other by means of connecting portions formed so as to pass through the insulating layer; and the connecting portion comprises a part of the wiring layer which is extended into a region of an opening formed so as to pass through said insulating layer and a low-melting point metal disposed in the opening and electrically connecting the part of the wiring layer with a wiring substrate formed on an adjacent insulating layer of the laminated structure.
摘要翻译：多层布线基板包括：多个布线基板，每个基板包括板或片状绝缘层和仅形成在绝缘层的一个表面上的布线层; 所述多个布线基板以使得所述绝缘层和布线层交替布置的方式层叠; 布置在绝缘层的各个表面上的至少一对所述布线层通过形成为穿过绝缘层的连接部彼此电连接; 并且所述连接部分包括延伸到形成为穿过所述绝缘层的开口的区域中的所述布线层的一部分和布置在所述开口中的低熔点金属，并且将所述布线层的所述部分与形成在叠层结构的相邻绝缘层上的布线基板。

4. 发明授权

US06455786B1 Wiring board and manufacturing method thereof and semiconductor device 有权
标题翻译：接线板及其制造方法及半导体器件
公开(公告)号：US06455786B1
公开(公告)日：2002-09-24
申请号：US09539117
申请日：2000-03-30
申请人： Michio Horiuchi , Shigetsugu Muramatsu , Shigeru Mizuno , Takashi Kurihara
发明人： Michio Horiuchi , Shigetsugu Muramatsu , Shigeru Mizuno , Takashi Kurihara
IPC分类号： H05K116
CPC分类号： H01L23/3114 , H01L23/3107 , H01L23/49827 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A wiring board and electrode of a semiconductor element are connected with each other by the method of wire bonding, and problems arising from the thermal stress generated in the process of mounting are overcome. There is provided a wiring board comprising: a first face joined to an electrode forming face of a semiconductor element 10; and a second face on the opposite side of the first face, a wiring pattern 16 being formed on the second face, a land 24 joined to an external connecting terminal 22 being formed at one end of the wiring pattern, a wire bonding section 16a connected with a bonding wire 40 being formed at the other end of the wiring pattern, wherein the land 24 is supported by a buffer layer 34 for reducing the thermal stress generated when the semiconductor element, to which the wiring board is attached, is mounted via the external connecting terminals, and the wire bonding section 16a is supported by a bonding support layer 36 having an elastic modulus capable of allowing wire bonding.
摘要翻译：半导体元件的布线基板和电极通过引线接合的方式相互连接，克服了在安装过程中产生的热应力引起的问题。提供了一种布线板，包括：连接到半导体元件10的电极形成面的第一面; 和在第一面的相对侧的第二面，形成在第二面上的布线图案16，形成在布线图案的一端的与外部连接端子22接合的台面24，连接有引线接合部16a 其中接合线40形成在布线图案的另一端，其中，台肩24由缓冲层34支撑，用于减小当安装有布线板的半导体元件经由外部连接端子和引线接合部分16a由具有能够引线接合的弹性模量的接合支撑层36支撑。

5. 发明授权

US06407460B1 Multilayer circuit board 有权
标题翻译：多层电路板
公开(公告)号：US06407460B1
公开(公告)日：2002-06-18
申请号：US09616139
申请日：2000-07-13
申请人： Michio Horiuchi , Shigeru Mizuno
发明人： Michio Horiuchi , Shigeru Mizuno
IPC分类号： H01L2352
CPC分类号： H01L23/49838 , H01L2224/16 , H01L2224/16235 , H01L2924/15174 , H01L2924/15311 , H05K1/112 , H05K2201/09227 , H05K2201/10734
摘要： The present invention provides a multilayer circuit board for mounting thereon a semiconductor chip or other electronic elements having electrode terminals or other connection terminals which are arranged in a grid, staggered, or close-packed manner in an improved form to enable reduction in the number of the wiring layers for lead wiring lines, thereby facilitating the production of multilayer circuit boards and providing an improved product reliability. The multilayer circuit board comprises: a base board having a mounting surface for mounting thereon a semiconductor chip and/or other electronic elements having lattice-arranged connection terminals; connection terminal pads arranged on the mounting surface to form a plane lattice corresponding to the lattice arrangement of the connection terminals and having lattice sites each occupied by one of the connection terminal pads; lead wiring lines lying on the mounting surface and having one end connected to the connection terminal pads and the other end extending outwardly from the plane lattice; and the said plane lattice having a peripheral zone including periodic vacant lattice areas formed by vacant lattice sites occupied by no connection terminal pads.
摘要翻译：本发明提供了一种多层电路板，用于在其上安装半导体芯片或具有电极端子或其他连接端子的其他电子元件，电子端子或其他连接端子以改进的形式布置成格栅，交错或紧密堆叠的方式，以减少数量用于引线布线的布线层，从而便于生产多层电路板并提供改进的产品可靠性。多层电路板包括：基板，其具有用于安装其上的半导体芯片的安装表面和/或具有格子排列的连接端子的其它电子元件; 连接端子焊盘，其布置在所述安装表面上以形成与所述连接端子的格栅布置相对应的平面格子，并具有各自由所述连接端子焊盘之一占据的格子部位; 引线布线位于安装表面上，其一端连接到连接端子焊盘，另一端从平面格架向外延伸; 并且所述平面晶格具有包括由没有连接端子焊盘占据的空位网格形成的周期性空格格区域的周边区域。

6. 发明授权

US06660942B2 Semiconductor device with an exposed external-connection terminal 失效
标题翻译：具有暴露的外部连接端子的半导体器件
公开(公告)号：US06660942B2
公开(公告)日：2003-12-09
申请号：US09826512
申请日：2001-04-05
申请人： Michio Horiuchi , Takashi Kurihara
发明人： Michio Horiuchi , Takashi Kurihara
IPC分类号： H05K103
CPC分类号： H05K3/4694 , H01L23/3735 , H01L23/49822 , H01L23/49894 , H01L2224/05567 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2224/73204 , H01L2924/01078 , H01L2924/01079 , H05K1/0271 , H05K1/114 , H05K3/4652 , H05K3/4655 , H05K2201/0133 , H05K2201/0187 , H05K2201/0195 , H05K2201/09972 , Y10T428/24942 , Y10T428/2495 , H01L2924/00014
摘要： A wiring substrate equipped with a rerouted wiring having one end connected to an electronic-part mounting pad for electrically connecting an electronic part and another end connected to an external-connection terminal. In the wiring substrate, a low-elasticity underlayer made of a material having a lower modulus of elasticity than that of a base material of the wiring substrate is disposed between the base material of the wiring substrate and each of the electronic-part mounting pad and the rerouted wiring. A method of manufacturing the wiring substrate and a semiconductor device using the wiring substrate are also disclosed.
摘要翻译：一种布线基板，其配备有重新布线的布线，其一端连接到用于电连接电子部件的电子部件安装焊盘和连接到外部连接端子的另一端。在布线基板中，在布线基板的基材和电子部件安装用基板的每一个之间配置有由比布线基板的基材低的弹性模量的材料制成的低弹性底层，重新布线。还公开了制造布线基板的方法和使用该布线基板的半导体器件。

7. 发明授权

US06407344B1 Multilayer circuit board 有权
标题翻译：多层电路板
公开(公告)号：US06407344B1
公开(公告)日：2002-06-18
申请号：US09631397
申请日：2000-08-03
申请人： Michio Horiuchi , Takashi Kurihara
发明人： Michio Horiuchi , Takashi Kurihara
IPC分类号： H01R909
CPC分类号： H05K1/112 , H01L23/49838 , H01L23/5386 , H01L2224/16 , H01L2224/16235 , H01L2924/01019 , H01L2924/15174 , H01L2924/15311 , H05K2201/09227 , H05K2201/10734
摘要： A multilayer circuit board comprising a plurality of laminated routing layers, which is used to mount thereon an electronic part, such as a semiconductor chip or device, provided with electrodes formed in a certain pattern, each of the routing layers being provided with lands and routing lines on its surface, the lands being arranged to conform to the pattern of the electrodes of the electronic part, and the routing line being connected at its end to the land, and being routed toward the outside from a region where the lands are arranged, wherein the lands on each of the routing layers are arranged to have a pattern in which a closed virtual line formed by consecutively linking the peripheral lands at least partially has concave sections. Preferably, the concave section is in the form of a rectangular equilateral triangle, and the peripheral lands are located along the sides of the rectangular equilateral triangle. Alternatively, the concave section may be in the form of a pseudo-rectangular equilateral triangle having a rectangular vertex at which one of the peripheral lands is located, and a cutout at an intersection of its hypotenuse and one of equilaterals. The multilayer circuit board has a reduced number of routing layers relative to conventional multilayer circuit boards, and can be produced with an increased yield and high reliability.
摘要翻译：一种多层电路板，包括多个层压路由层，其用于在其上安装诸如半导体芯片或器件的电子部件，其设置有以特定图案形成的电极，每个路由层设置有焊盘和布线其表面上的线条被布置成符合电子部件的电极的图案，并且布线线在其端部连接到平台，并且从布置的区域被引导到外部，其中每个所述布线层上的焊盘被布置成具有其中通过连续地连接所述外围焊盘形成的闭合虚拟线至少部分地具有凹形部分的图案。优选地，凹部为矩形等边三角形的形式，并且外围平台沿着矩形等边三角形的侧面定位。或者，凹部可以是具有矩形顶点的伪矩形等边三角形的形式，在该顶点处外围平台中的一个位于其上，并且在其斜边和其中一个平衡的交点处形成切口。多层电路板相对于常规多层电路板具有减少的布线层数，并且可以以增加的产量和高可靠性生产。

8. 发明授权

US06469260B2 Wiring boards, semiconductor devices and their production processes 有权
标题翻译：接线板，半导体器件及其生产工艺
公开(公告)号：US06469260B2
公开(公告)日：2002-10-22
申请号：US09792991
申请日：2001-02-24
申请人： Michio Horiuchi , Takashi Kurihara
发明人： Michio Horiuchi , Takashi Kurihara
IPC分类号： H01R909
CPC分类号： H01L21/568 , H01L21/4832 , H01L21/4885 , H01L21/6835 , H01L23/13 , H01L23/4952 , H01L23/49541 , H01L23/49816 , H01L23/49861 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/81 , H01L2224/13111 , H01L2224/16225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45157 , H01L2224/45164 , H01L2224/45565 , H01L2224/45572 , H01L2224/45599 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/48699 , H01L2224/49 , H01L2224/81801 , H01L2224/85444 , H01L2224/8592 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/3011 , H01L2924/30111 , H05K3/20 , H05K2201/10287 , H05K2201/10977 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A wiring board comprising a substrate having applied on the same side surface thereof one or more terminals for connecting a semiconductor element and one or more terminals for external connection, in which the terminals for connecting the semiconductor element and the terminals for external connection are electrically connected, by a wire, with each other in the interior of the wiring board, and a semiconductor device comprising the wiring board having packaged thereon semiconductor elements. Processes for the production of the wiring board and the semiconductor device are also disclosed.
摘要翻译：一种布线基板，其特征在于，具有与上述半导体元件连接的半导体元件的一个或多个端子和一个以上的外部连接端子连接的半导体元件用端子和外部连接端子电连接的同一侧面的基板通过导线彼此连接在布线板的内部，以及半导体器件，包括其上封装有半导体元件的布线板。还公开了用于制造布线板和半导体器件的工艺。

9. 发明授权

US06731010B2 Resin sealed stacked semiconductor packages with flat surfaces 失效
标题翻译：树脂密封堆叠半导体封装与平面
公开(公告)号：US06731010B2
公开(公告)日：2004-05-04
申请号：US09922872
申请日：2001-08-06
申请人： Michio Horiuchi , Takashi Kurihara
发明人： Michio Horiuchi , Takashi Kurihara
IPC分类号： H01L2302
CPC分类号： H01L23/02 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/3107 , H01L23/49816 , H01L24/48 , H01L2221/68377 , H01L2224/05599 , H01L2224/16225 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/73204 , H01L2224/73265 , H01L2224/85001 , H01L2224/85399 , H01L2224/92125 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/18161 , H01L2924/18165 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device which reduces and simultaneously achieves a uniform mounting height, does not require complicated steps for mounting individual chips, improves the manufacturing yield, achieves a uniform height of the semiconductor device without being affected by the variation in thickness of the chips, and enables execution of electrical tests all together and a process for production of the same, wherein a semiconductor chip is housed, with its active surface facing upward, in a through hole of a printed circuit board provided with an interconnection pattern on its top surface, electrode terminals of the active surface are connected to the interconnection pattern by bonding wires, a sealing resin layer seals the bonding wires and semiconductor chip together and fixes the semiconductor chip in the through hole, and the bottom surface of the printed circuit board, the downward facing back surface of the semiconductor chip, and the bottom surface of the sealing resin layer are finished to the same flat surface by grinding and polishing.
摘要翻译：减少并同时实现均匀安装高度的半导体器件不需要用于安装单个芯片的复杂步骤，提高制造成品率，在不受芯片厚度变化的影响的情况下实现半导体器件的均匀高度，并且使得一起执行电气测试及其制造方法，其中将半导体芯片的活性表面朝上放置在其顶表面上具有互连图案的印刷电路板的通孔中，电极端子的活性表面通过接合线连接到互连图案，密封树脂层将接合线和半导体芯片一起密封在一起，并将半导体芯片固定在通孔中，并且印刷电路板的底表面向下的背面半导体芯片的表面和密封树脂层的底面为f 通过磨削和抛光成为相同的平面。

10. 发明授权

US06522017B2 Wiring board and semiconductor device 有权
标题翻译：接线板和半导体器件
公开(公告)号：US06522017B2
公开(公告)日：2003-02-18
申请号：US09797887
申请日：2001-03-02
申请人： Michio Horiuchi , Takashi Kurihara
发明人： Michio Horiuchi , Takashi Kurihara
IPC分类号： H01L2348
CPC分类号： H01L24/81 , H01L21/563 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L24/29 , H01L2224/1134 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/1579 , H01L2924/181 , H05K1/112 , H05K3/3436 , H05K3/3463 , H05K2201/0394 , H05K2201/09472 , H05K2201/10674 , Y02P70/613 , H01L2924/00 , H01L2924/00014 , H01L2924/0665
摘要： Wiring board having a wiring layer to which electronic components are electrically connected, in through-holes closed at one of the ends thereof by the wiring layer are formed at predetermined positions of the wiring board, and a low melting point metal for electrically connecting the wiring layer to the electronic components is filled into the through-holes, and a semiconductor device using the same. The production methods of the wiring board and the semiconductor device are also disclosed.
摘要翻译：在布线基板的规定位置形成具有电连接电路的布线层的布线层，其布线基板的一个端部封闭的贯通孔，布线基板的电气连接用的低熔点金属电子部件的层被填充到通孔中，以及使用其的半导体器件。还公开了布线板和半导体器件的制造方法。

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