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    • 4. 发明授权
    • High-speed interconnection adapter having automated crossed differential pair correction
    • 具有自动交叉差分对校正的高速互连适配器
    • US06865231B1
    • 2005-03-08
    • US09597192
    • 2000-06-20
    • William P. BuntonJohn KrausePatricia L. Whiteside
    • William P. BuntonJohn KrausePatricia L. Whiteside
    • H04L25/34
    • H04L25/085
    • An adapter configured to automatically detect and compensate for differential signal inversion is herein disclosed. In one embodiment, the adapter is part of a computer network having differential conductor pairs conveying differential signals between network devices. The network devices include adapters coupled to transmit and receive signals via the differential conductor pairs. The adapter preferably includes a lane receiver, a decoder, and a synchronization circuit. The lane receiver is configured to receive a single differential signal and to convert the differential signal into a sequence of code symbols. The decoder decodes the code symbols to produce a sequence of received symbols. The synchronization circuit examines the sequence of received symbols to determine if it is incorrect due to inversion of the differential signal, and if so, it causes the lane receiver to correct for the differential signal inversion. It is expected that the received symbol sequence will include a training symbol sequence which will have a start symbol whose decoded value is unaffected by differential signal inversion, and a training symbol whose decoded value is indicative of the presence or absence of invasion. The synchronization circuit, upon identifying the training sequence, will thus be able to determine whether inversion exists and be able to automatically correct for it.
    • 本文公开了一种被配置为自动检测和补偿差分信号反相的适配器。 在一个实施例中,适配器是具有在网络设备之间传送差分信号的差分导体对的计算机网络的一部分。 网络设备包括耦合到经由差分导体对发送和接收信号的适配器。 适配器优选地包括通道接收器,解码器和同步电路。 车道接收器被配置为接收单个差分信号并且将差分信号转换成代码符号序列。 解码器对码符号进行解码以产生接收符号的序列。 同步电路检查接收到的符号的序列,以确定由于差分信号的反相而不正确,如果是,则使得通道接收机校正差分信号反相。 预期所接收的符号序列将包括训练符号序列,该训练符号序列将具有其解码值不受差分信号反相影响的起始符号,以及其解码值表示存在或不存在入侵的训练符号。 因此,同步电路在识别训练序列时将能够确定反转是否存在并能够自动校正。
    • 6. 发明授权
    • High-speed interconnection link having automated lane reordering
    • 具有自动车道重新排序的高速互连链路
    • US06961347B1
    • 2005-11-01
    • US09597190
    • 2000-06-20
    • William P. BuntonJohn KrausePatricia L. Whiteside
    • William P. BuntonJohn KrausePatricia L. Whiteside
    • H04J3/16H04L25/14
    • H04L25/14
    • A multi-lane link that automatically detects if the lanes in the link have been reordered and corrects the order of the lanes. In one embodiment, the link includes a transmitter and a receiver. The receiver is configured to receive a plurality of lanes and includes a receiver logic circuit configured to receive signals from each of the plurality of lanes. Lane misordering is corrected during a training sequence in which a first training sequence and a second training sequence are bilaterally transmitted between the transmitter and receiver. The receiver monitors the training sequence for symbols that are unique to each lane and if an unexpected symbol is detected in the lane, the receiver logic circuit will correct the order of the lanes. The link further comprises a transmitter logic circuit configured to transmit signals to the lanes. The transmitter logic circuit is configured to reorder the sequence of the signals transmitted to the lanes if the transmitter does not detect a response from the receiver. The transmitter logic circuit may consist of a bank of multiplexers configured to transmit a selected one of two input signals to be transmitted through a lane. Similarly, the receiver logic circuit may comprises a bank of multiplexers configured to transmit a selected one of two input signals received from a lane. The unique lane identifiers symbols are preferably insensitive to binary inversion and are preferably 10-bit symbols compatible with an 8B/10B encoding scheme.
    • 一个多通道链接,可以自动检测链路中的通道是否重新排序,并纠正通道的顺序。 在一个实施例中,链路包括发射机和接收机。 接收机被配置为接收多个车道,并且包括被配置为从多个车道中的每一条车道接收信号的接收机逻辑电路。 在训练序列期间校正车道排序,其中第一训练序列和第二训练序列在发射机和接收机之间被双向传输。 接收机监视每个通道唯一的符号的训练序列,如果在通道中检测到意外符号,则接收机逻辑电路将校正车道的顺序。 该链路还包括被配置为向车道传输信号的发射机逻辑电路。 发射机逻辑电路被配置为如果发射机未检测到来自接收机的响应,则重新排序发送到车道的信号的序列。 发射机逻辑电路可以由一组多路复用器组成,其被配置为发送要通过车道传输的两个输入信号中的所选择的一个。 类似地,接收器逻辑电路可以包括一组复用器,其被配置为发送从通道接收的两个输入信号中选择的一个。 唯一的车道标识符符号优选地对二进制反转不敏感,并且优选地是与8B / 10B编码方案兼容的10位符号。