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1. 发明授权

US06849554B2 Method of etching a deep trench having a tapered profile in silicon 失效
标题翻译：在硅中蚀刻具有锥形轮廓的深沟槽的方法
公开(公告)号：US06849554B2
公开(公告)日：2005-02-01
申请号：US10137176
申请日：2002-05-01
申请人： Michael Rattner , Jeffrey D. Chinn
发明人： Michael Rattner , Jeffrey D. Chinn
IPC分类号： H01L21/3065 , H01L21/762 , H01L21/302
CPC分类号： H01L21/3065 , H01L21/76232
摘要： Disclosed herein is a method of etching deep trenches in a substrate which utilizes the overlying mask structure to achieve a trench having a positive tapered sidewall angle of less than about 88°. The method employs the successive etching of a lateral undercut in the substrate beneath a masking material, while at the same time etching vertically downward beneath the mask. The coordinated widening of the lateral undercut at the top of the trench, while vertically extending the depth of the trench, is designed to provide the desired trench sidewall taper angle.
摘要翻译：本文公开了一种蚀刻衬底中的深沟槽的方法，其利用上覆掩模结构来实现具有小于约88°的正锥形侧壁角的沟槽。该方法采用在掩模材料下面的衬底中的横向底切的连续蚀刻，同时在掩模下垂直向下蚀刻。在沟槽顶部的横向底切的协调加宽，同时垂直延伸沟槽的深度，被设计成提供所需的沟槽侧壁锥角。

2. 发明授权

US07618548B2 Silicon-containing structure with deep etched features, and method of manufacture 失效
标题翻译：具有深蚀刻特征的含硅结构及其制造方法
公开(公告)号：US07618548B2
公开(公告)日：2009-11-17
申请号：US11214121
申请日：2005-08-29
申请人： Jeffrey D. Chinn , Michael Rattner , Nicholas Pornsin-Sirirak , Yanping Li
发明人： Jeffrey D. Chinn , Michael Rattner , Nicholas Pornsin-Sirirak , Yanping Li
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/30655
摘要： We have developed an uncomplicated method of plasma etching deeply recessed features such as deep trenches, of at least 5 μm in depth, in a silicon-containing substrate, in a manner which generates smooth sidewalls, having a roughness of less than about 1 μm, typically less than about 500 nm, and even more typically between about 100 nm and 20 nm. Features having a sidewall taper angle, relative to an underlying substrate, typically ranges from about 85° to about 92° and exhibiting the smooth sidewalls are produced by the method. In one embodiment, a stabilizing etchant species is used constantly during the plasma etch process, while at least one other etchant species and at least one polymer depositing species are applied intermittently, typically periodically, relative to each other. In another embodiment, the stabilizing etchant species is used constantly and a mixture of the other etchant species and polymer depositing species is used intermittently.
摘要翻译：我们已经开发出一种不复杂的方法，其以产生平滑侧壁，粗糙度小于约1μm的方式，在含硅衬底中等深度蚀刻深凹陷特征，例如至少5μm深的深沟槽，通常小于约500nm，甚至更典型地在约100nm和20nm之间。具有相对于下面的基底的侧壁锥角的特征通常在约85°至约92°的范围内，并且通过该方法产生了平滑的侧壁。在一个实施例中，在等离子体蚀刻过程期间不断地使用稳定蚀刻剂物质，而至少一种其它蚀刻剂物质和至少一种聚合物沉积物质相对于彼此间歇地，典型地周期性地施加。在另一个实施方案中，稳定化蚀刻剂物质被不断使用，并且间歇地使用其它蚀刻剂物质和聚合物沉积物质的混合物。

3. 发明授权

US07074723B2 Method of plasma etching a deeply recessed feature in a substrate using a plasma source gas modulated etchant system 失效
标题翻译：使用等离子体源气体调制蚀刻剂系统等离子体蚀刻衬底中的深凹陷特征的方法
公开(公告)号：US07074723B2
公开(公告)日：2006-07-11
申请号：US10210929
申请日：2002-08-02
申请人： Jeffrey D. Chinn , Michael Rattner , Nicholas Pornsin-Sirirak , Yanping Li
发明人： Jeffrey D. Chinn , Michael Rattner , Nicholas Pornsin-Sirirak , Yanping Li
IPC分类号： H01L21/302
CPC分类号： H01L21/30655
摘要： We have developed an uncomplicated method of plasma etching deeply recessed features such as deep trenches, of at least 5 μm in depth, in a silicon-containing substrate, in a manner which generates smooth sidewalls, having a roughness of less than about 1 μm, typically less than about 500 nm, and even more typically between about 100 nm and 20 nm. Features having a sidewall taper angle, relative to an underlying substrate, typically ranges from about 85° to about 92° and exhibiting the smooth sidewalls are produced by the method. In one embodiment, a stabilizing etchant species is used constantly during the plasma etch process, while at least one other etchant species and at least one polymer depositing species are applied intermittently, typically periodically, relative to each other. In another embodiment, the stabilizing etchant species is used constantly and a mixture of the other etchant species and polymer depositing species is used intermittently.
摘要翻译：我们已经开发出一种不复杂的方法，其以产生平滑侧壁，粗糙度小于约1μm的方式，在含硅衬底中等深度蚀刻深凹陷特征，例如至少5μm深的深沟槽，通常小于约500nm，甚至更典型地在约100nm和20nm之间。具有相对于下面的基底的侧壁锥角的特征通常在约85°至约92°的范围内，并且通过该方法产生了平滑的侧壁。在一个实施例中，在等离子体蚀刻过程期间不断地使用稳定蚀刻剂物质，而至少一种其它蚀刻剂物质和至少一种聚合物沉积物质相对于彼此间歇地，典型地周期性地施加。在另一个实施方案中，稳定化蚀刻剂物质被不断使用，并且间歇地使用其它蚀刻剂物质和聚合物沉积物质的混合物。

4. 发明授权

US06846746B2 Method of smoothing a trench sidewall after a deep trench silicon etch process 失效
标题翻译：在深沟槽硅蚀刻工艺之后平滑沟槽侧壁的方法
公开(公告)号：US06846746B2
公开(公告)日：2005-01-25
申请号：US10137543
申请日：2002-05-01
申请人： Michael Rattner , Jeffrey D. Chinn
发明人： Michael Rattner , Jeffrey D. Chinn
IPC分类号： B81C1/00 , H01L21/3065 , H01L21/302
CPC分类号： B81C1/00611 , B81B2203/033 , B81C2201/0126 , B81C2201/0178 , H01L21/3065 , H01L21/30655
摘要： Disclosed herein is a method of smoothing a trench sidewall after a deep trench silicon etch process which minimizes sidewall scalloping present after the silicon trench etch. The method comprises exposing the silicon trench sidewall to a plasma generated from a fluorine-containing gas, at a process chamber pressure within the range of about 1 mTorr to about 30 mTorr, for a time period within the range of about 10 seconds to about 600 seconds. A substrate bias voltage within the range of about −10 V to about −40 V is applied during the performance of the post-etch treatment method of the invention.
摘要翻译：这里公开了一种在深沟槽硅蚀刻工艺之后平滑沟槽侧壁的方法，其最小化在硅沟槽蚀刻之后存在的侧壁扇形。该方法包括将硅沟槽侧壁暴露于在约1mTorr至约30mTorr范围内的处理室压力下从含氟气体产生的等离子体，时间范围为约10秒至约600 秒。在本发明的蚀刻后处理方法的执行期间，施加约-10V至约-40V范围内的衬底偏置电压。

5. 发明授权

US09725805B2 Apparatus and method for controlled application of reactive vapors to produce thin films and coatings 有权
公开(公告)号：US09725805B2
公开(公告)日：2017-08-08
申请号：US11445706
申请日：2006-06-02
申请人： Boris Kobrin , Romuald Nowak , Richard C. Yi , Jeffrey D. Chinn
发明人： Boris Kobrin , Romuald Nowak , Richard C. Yi , Jeffrey D. Chinn
IPC分类号： C23C16/448 , C23C16/455 , B05D1/00 , B82Y30/00 , B05D3/14
CPC分类号： C23C16/45557 , B05D1/60 , B05D3/142 , B82Y30/00 , C23C16/4485 , C23C16/45561
摘要： A vapor phase deposition method and apparatus for the application of thin layers and coatings on substrates. The method and apparatus are useful in the fabrication of electronic devices, micro-electromechanical systems (MEMS), Bio-MEMS devices, micro and nano imprinting lithography, and microfluidic devices. The apparatus used to carry out the method provides for the addition of a precise amount of each of the reactants to be consumed in a single reaction step of the coating formation process. The apparatus provides for precise addition of quantities of different combinations of reactants during a single step or when there are a number of different individual steps in the coating formation process. The precise addition of each of the reactants in vapor form is metered into a predetermined set volume at a specified temperature to a specified pressure, to provide a highly accurate amount of reactant.

6. 发明授权

US07638167B2 Controlled deposition of silicon-containing coatings adhered by an oxide layer 有权
标题翻译：由氧化物层附着的含硅涂层的控制沉积
公开(公告)号：US07638167B2
公开(公告)日：2009-12-29
申请号：US10862047
申请日：2004-06-04
申请人： Boris Kobrin , Romuald Nowak , Richard C. Yi , Jeffrey D. Chinn
发明人： Boris Kobrin , Romuald Nowak , Richard C. Yi , Jeffrey D. Chinn
IPC分类号： C23C16/00 , C23C14/10
CPC分类号： B82Y30/00 , C23C16/0227 , C23C16/402
摘要： We have developed an improved vapor-phase deposition method and apparatus for the application of films/coatings on substrates. The method provides for the addition of a precise amount of each of the reactants to be consumed in a single reaction step of the coating formation process. In addition to the control over the amount of reactants added to the process chamber, the present invention requires precise control over the total pressure (which is less than atmospheric pressure) in the process chamber, the partial vapor pressure of each vaporous component present in the process chamber, the substrate temperature, and typically the temperature of a major processing surface within said process chamber. Control over this combination of variables determines a number of the characteristics of a film/coating or multi-layered film/coating formed using the method. By varying these process parameters, the roughness and the thickness of the films/coatings produced can be controlled.
摘要翻译：我们已经开发了一种改进的气相沉积方法和装置，用于在基底上施加膜/涂层。该方法提供在涂层形成过程的单个反应步骤中添加精确量的每种待消耗的反应物。除了控制添加到处理室中的反应物的量之外，本发明需要精确控制处理室中的总压力（其小于大气压），存在于处理室中的每种气态组分的部分蒸气压处理室，衬底温度以及典型地在所述处理室内的主处理表面的温度。对这种变量组合的控制决定了使用该方法形成的膜/涂层或多层膜/涂层的许多特性。通过改变这些工艺参数，可以控制所生产的膜/涂层的粗糙度和厚度。

7. 发明授权

US06900133B2 Method of etching variable depth features in a crystalline substrate 失效
标题翻译：在晶体衬底中蚀刻可变深度特征的方法
公开(公告)号：US06900133B2
公开(公告)日：2005-05-31
申请号：US10247467
申请日：2002-09-18
申请人： Jeffrey D. Chinn , Michael B. Rattner , James A. Cooper , Rolf A. Guenther
发明人： Jeffrey D. Chinn , Michael B. Rattner , James A. Cooper , Rolf A. Guenther
IPC分类号： B81C1/00 , H01L21/3065 , H01L21/308 , H01L21/302
CPC分类号： B81C1/00626 , B81B2201/0214 , B81B2201/058 , B81C99/009 , B81C2201/0132 , H01L21/3065 , H01L21/3081
摘要： Disclosed herein is an easy and well-integrated method of etching features to different depths in a crystalline substrate, such as a single-crystal silicon substrate. The method utilizes a specialized masking process and takes advantage of a highly selective etch process. The method provides a system of interconnected, variable depth reservoirs and channels. The plasma used to etch the channels may be designed to provide a sidewall roughness of about 200 nm or less. The resulting structure can be used in various MEMS applications, including biomedical MEMS and MEMS for semiconductor applications.
摘要翻译：本文公开了一种在晶体衬底（例如单晶硅衬底）中对不同深度蚀刻特征的易于且良好集成的方法。该方法利用专门的掩蔽过程并利用高选择性蚀刻工艺。该方法提供了一个互连的，可变深度的储层和通道的系统。用于蚀刻通道的等离子体可以设计成提供约200nm或更小的侧壁粗糙度。所得结构可用于各种MEMS应用，包括用于半导体应用的生物医学MEMS和MEMS。

8. 发明授权

US06887732B2 Microstructure devices, methods of forming a microstructure device and a method of forming a MEMS device 失效
标题翻译：微结构器件，形成微结构器件的方法和形成MEMS器件的方法
公开(公告)号：US06887732B2
公开(公告)日：2005-05-03
申请号：US09850951
申请日：2001-05-07
申请人： Vidyut Gopal , Jeffrey D. Chinn
发明人： Vidyut Gopal , Jeffrey D. Chinn
IPC分类号： B81B3/00 , H01L21/00
CPC分类号： B81C1/00166 , B81B2203/0118
摘要： Microstructure devices, methods of forming a microstructure device and a method of forming a MEMS device are described. According to one aspect, a microstructure device includes: a semiconductive substrate; a monolithic microstructure device feature coupled with the semiconductive substrate, and wherein at least a portion of the microstructure device feature is configured to move relative to the semiconductive substrate; and a conductive structure provided directly upon the microstructure device feature.
摘要翻译：描述微结构器件，形成微结构器件的方法和形成MEMS器件的方法。根据一个方面，微结构器件包括：半导体衬底; 与所述半导体衬底耦合的单片微结构器件特征，并且其中所述微结构器件特征的至少一部分被配置为相对于所述半导体衬底移动; 以及直接设置在微结构器件特征上的导电结构。

9. 发明授权

US06830950B2 Integrated method for release and passivation of MEMS structures 失效
标题翻译： MEMS结构的释放和钝化的集成方法
公开(公告)号：US06830950B2
公开(公告)日：2004-12-14
申请号：US10300970
申请日：2002-11-20
申请人： Jeffrey D. Chinn , Rolf A. Guenther , Michael B. Rattner , James A. Cooper , Toi Yue Becky Leung
发明人： Jeffrey D. Chinn , Rolf A. Guenther , Michael B. Rattner , James A. Cooper , Toi Yue Becky Leung
IPC分类号： H01L2100
CPC分类号： B81C1/0096 , B81B3/0005 , B81C2201/0176 , B81C2201/112 , B82Y30/00
摘要： Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises pretreating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures.
摘要翻译：本文公开了一种改进疏水性自组装单层（SAM）涂层到MEMS结构表面的粘附性的方法，以防止粘结。该方法包括用包含氧气和任选的氢气的源气体产生的等离子体来预处理MEMS结构的表面。处理氧化表面，然后与氢气反应以在表面上形成键合的OH基团。氢源可以作为等离子体源气体的一部分存在，使得在用等离子体处理表面期间产生结合的OH基团。本文还公开了一种用于MEMS结构的释放和钝化的集成方法。

10. 发明授权

US06599842B2 Method for rounding corners and removing damaged outer surfaces of a trench 失效
标题翻译：用于对角落进行倒角并去除损坏的沟槽外表面的方法
公开(公告)号：US06599842B2
公开(公告)日：2003-07-29
申请号：US09450475
申请日：1999-11-29
申请人： John Chao , Mohit Jain , Jeffrey D. Chinn
发明人： John Chao , Mohit Jain , Jeffrey D. Chinn
IPC分类号： H01L21302
CPC分类号： H01L21/67069 , H01L21/3065
摘要： A method for processing a substrate disposed in a substrate processing chamber to modify the contour of a trench formed on the substrate. The substrate processing chamber is the type that has a coil and a plasma generation system including a source power system operatively coupled to the coil and a bias power system operatively coupled to the substrate process chamber. The method includes transferring the substrate into the substrate process chamber. Thereafter, the substrate is exposed to a plasma formed from a first process gas consisting essentially of a sputtering agent by applying RF energy from the source power system to the coil. The plasma is biased toward the substrate by applying bias power to the substrate process chamber. Thereafter, the substrate is exposed to a plasma formed from a second process gas without applying bias power or applying minimal bias power to the substrate process chamber.
摘要翻译：一种用于处理设置在基板处理室中以改变形成在基板上的沟槽的轮廓的基板的方法。衬底处理室是具有线圈和等离子体产生系统的类型，其包括可操作地耦合到线圈的源电力系统和可操作地耦合到衬底处理室的偏置电力系统。该方法包括将衬底转移到衬底处理室中。此后，通过将来自源电力系统的RF能量施加到线圈，将衬底暴露于由基本上由溅射剂组成的第一工艺气体形成的等离子体。通过向衬底处理室施加偏置功率将等离子体偏压到衬底。此后，将衬底暴露于由第二工艺气体形成的等离子体，而不施加偏置功率或向衬底处理室施加最小的偏置功率。

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