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1. 发明授权

US06496890B1 Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters 有权
标题翻译：采用与多个总线主机的共享总线接口的数据通信系统的总线挂起预防和恢复
公开(公告)号：US06496890B1
公开(公告)日：2002-12-17
申请号：US09454681
申请日：1999-12-03
申请人： Michael Joseph Azevedo , Brent Cameron Beardsley , Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Brent Cameron Beardsley , Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F1300
CPC分类号： G06F13/4036 , G06F13/28
摘要： A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. Some of the masters are associated with the external bus and others are associated with the internal bus, and one of the bus masters is a control master associated with the internal processor. The scheme utilizes a shared bus hang prevention and recovery device having a circuitry and a control code. The circuitry is timing each pending request of the control master for the shared bus and initiating bus recovery if the shared bus is hung up, when the control master exceeded a pre-determined time period allowed for waiting to acquire the shared bus control and complete the transfer on the shared bus. The control code is used for monitoring and controlling the circuitry and terminating the transfer in progress causing the shared bus hang-up. During the bus recovery the circuitry prevents bus request grants to the master attached to the external bus until the master subsequent reset, and the control program instructions initiates transfers for all pending requests for the shared bus from the control master queue. Each transfer is being timed and terminated if the shared bus is hung up again. Upon the control master queue clearing, the internal processor executes the control program instructions to reset and reinitialize all masters and slaves on the shared bus.
摘要翻译：提供了一种用于数据通信系统的共享总线挂起预防和恢复方案，其中共享总线连接到多个总线主机和相应的从站，并且位于连接到系统处理器的外部总线与连接到系统处理器的内部总线之间内部处理器一些主机与外部总线相关，其他主机与内部总线相关，其中一个总线主机是与内部处理器相关的控制主机。该方案利用具有电路和控制码的共享总线挂起防止和恢复装置。如果控制主机超过了允许等待获取共享总线控制的预定时间段并且完成了共享总线控制并且完成在共享总线上传输。控制代码用于监视和控制电路，并终止正在进行的传输，从而导致共享总线挂断。在总线恢复期间，电路阻止对连接到外部总线的主机的总线请求授权，直到主机后续复位，并且控制程序指令从控制主机队列开始对所有未决请求的共享总线的传输。如果共享总线再次挂起，则每次传输都将被定时和终止。当控制主队列清除时，内部处理器执行控制程序指令，以复位和重新初始化共享总线上的所有主机和从机。

2. 发明授权

US06606677B1 High speed interrupt controller 失效
标题翻译：高速中断控制器
公开(公告)号：US06606677B1
公开(公告)日：2003-08-12
申请号：US09520876
申请日：2000-03-07
申请人： Bitwoded Okbay , Andrew Dale Walls , Michael Joseph Azevedo
发明人： Bitwoded Okbay , Andrew Dale Walls , Michael Joseph Azevedo
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its scheme may be used for expanding the number of interrupts to be efficiently received and discriminated by a processor having a limited number of interrupt input lines. The present invention can be used for optimizing the management of data within a shared bus with multiple masters, wherein a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. The architecture utilizes the high speed interrupt controller device having a circuitry which has a plurality of interrupt lines and may have one output line and a control code, located in the device interrupt handler. The circuitry consists of a status register where an appropriate bit is set when an interrupt is received from an external interrupt source device, and an interrupt mask register which enables and disables certain interrupts. The control code is used for monitoring and controlling the circuitry and servicing the interrupts received by the processor.
摘要翻译：提供了一种用于数据通信系统的高速中断控制器和中断识别方案，可用于数据通信系统的子系统。控制器及其方案可以用于扩展有效接收和鉴别具有有限数量的中断输入线的处理器的中断数量。本发明可用于优化具有多个主机的共享总线内的数据管理，其中共享总线连接到多个总线主机和对应的从机，并且位于连接到系统处理器的外部总线与内部总线连接到内部处理器。该架构利用具有多个中断线的电路的高速中断控制器装置，并且可以具有位于设备中断处理器中的一个输出线和控制代码。该电路由一个状态寄存器组成，当外部中断源设备接收到一个中断时，该位置位适当位，中断屏蔽寄存器使能和禁止某些中断。控制代码用于监控和控制电路并为处理器接收的中断服务。

3. 发明授权

US07073030B2 Method and apparatus providing non level one information caching using prefetch to increase a hit ratio 失效
公开(公告)号：US07073030B2
公开(公告)日：2006-07-04
申请号：US10153966
申请日：2002-05-22
申请人： Michael Joseph Azevedo , Carol Spanel , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/0862 , G06F12/0897 , G06F2212/6024
摘要： A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1 instruction caching that uses prefetch to increase the hit ratio. Cache lines in a cache set are buffered, wherein the cache lines have a parameter indicating data selection characteristics associated with each buffered cache line. Then which buffered cache lines to cast out and/or invalidate is determined based upon the parameter indicating data selection characteristics.

4. 发明授权

US06519666B1 Arbitration scheme for optimal performance 失效
标题翻译：最优性能的仲裁方案
公开(公告)号：US06519666B1
公开(公告)日：2003-02-11
申请号：US09412990
申请日：1999-10-05
申请人： Michael Joseph Azevedo , Carol Spanel , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F13368
CPC分类号： G06F13/362
摘要： A shared bus arbitration scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and resources, some resources having higher priority than the others and including a peripheral device. Each master may request control of the shared bus and is adapted to perform short transfers and long burst transfers on the shared bus between a resource and the master. A shared bus arbiter is utilized for dynamically determining the highest priority request between a number of shared bus requests, and granting control of the shared bus to the highest priority requesting bus master. The arbiter utilizes a three-level priority hierarchy arbitration scheme where the highest priority level is given to short message transfer requests on the higher-priority system resources, the intermediate priority level is given to short message transfer requests on the lower-priority system resources, if there are no outstanding higher priority level requests, and the lowest priority level is given for long burst transfers, if there are no outstanding short message transfer requests.
摘要翻译：提供了一种用于数据通信系统的共享总线仲裁方案，其中共享总线连接到多个总线主机和资源，一些资源具有比其他资源更高的优先级，并且包括外围设备。每个主机可以请求对共享总线的控制，并且适于在资源和主机之间的共享总线上执行短传输和长突发传输。共享总线仲裁器用于动态地确定多个共享总线请求之间的最高优先级请求，以及授予对最高优先级请求总线主机的共享总线的控制。仲裁器采用三级优先级分级仲裁方案，其中优先级较高的优先级优先级较高优先级系统资源上的短消息传输请求，中间优先权级别给予低优先级系统资源上的短消息传输请求，如果没有突出的较高优先级请求，并且对于长突发传输给出最低优先级，则如果没有未完成的短消息传送请求。

5. 发明授权

US07035979B2 Method and apparatus for optimizing cache hit ratio in non L1 caches 有权
标题翻译：用于优化非L1高速缓存中的缓存命中率的方法和装置
公开(公告)号：US07035979B2
公开(公告)日：2006-04-25
申请号：US10154380
申请日：2002-05-22
申请人： Michael Joseph Azevedo , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Andrew Dale Walls
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026 , Y02D10/13
摘要： A method and apparatus for increasing the performance of a computing system and increasing the hit ratio in at least one non-L1 cache. A caching assistant and a processor are embedded in a processing system. The caching assistant analyzes system activity, monitors and coordinates data requests from the processor, processors and other data accessing devices, and monitors and analyzes data accesses throughout the cache hierarchy. The caching assistant is provided with a dedicated cache for storing fetched and prefetched data. The caching assistant improves the performance of the computing system by anticipating which data is likely to be requested for processing next, accessing and storing that data in an appropriate non-L1 cache prior to the data being requested by processors or data accessing devices. A method for increasing the processor performance includes analyzing system activity and optimizing a hit ratio in at least one non-L1 cache. The caching assistant performs processor data requests by accessing caches and monitoring the data requests to determine knowledge of the program code currently being processed and to determine if patterns of data accession exist. Based upon the knowledge gained through monitoring data accession, the caching assistant anticipates future data requests.
摘要翻译：一种用于增加计算系统的性能并增加至少一个非L1高速缓存中的命中率的方法和装置。缓存助理和处理器嵌入在处理系统中。缓存助理分析系统活动，监视和协调处理器，处理器和其他数据访问设备的数据请求，并监视和分析整个缓存层次结构中的数据访问。为缓存助手提供专用缓存，用于存储获取和预取数据。缓存助理通过预测下一个处理器或数据访问设备请求的数据之前可能要求哪个数据处理下一个访问和存储该数据到适当的非L1高速缓存中来改善计算系统的性能。一种用于增加处理器性能的方法包括分析系统活动并优化至少一个非L1高速缓存中的命中率。缓存助手通过访问高速缓存并监视数据请求来执行处理器数据请求，以确定当前正在处理的程序代码的知识，并确定是否存在数据存取模式。基于通过监视数据访问获得的知识，缓存助理预计未来的数据请求。

6. 发明授权

US06496878B1 Transfer progress alert module 失效
标题翻译：转移进度报警模块
公开(公告)号：US06496878B1
公开(公告)日：2002-12-17
申请号：US09432661
申请日：1999-11-03
申请人： Michael Joseph Azevedo , Roger Gregory Hathorn , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Roger Gregory Hathorn , Andrew Dale Walls
IPC分类号： G06F1328
CPC分类号： G06F13/32
摘要： A Transfer Progress Alert Module and a method for optimizing processing of a data transfer load, in a data communication system is provided. The data transfer load is divided in individual data blocks. The device and method simultaneously perform pipelined operations on different individual data blocks, thus optimizing the overlap of pipelined operations. The method includes initializing the transfer by selecting a pre-defined individual data block size and determining a key for selecting and monitoring transfers with transfer addresses within a pre-determined address region. The method then continuously repeats following steps until all monitored individual data blocks from the data transfer load are processed. First, the incoming individual data blocks are transferred on a bus between a peripheral device and a memory, and the Transfer Progress Alert module is used for monitoring the individual data blocks having transfer addresses determined to belong in the pre-determined address region. The TPA module is used to determine when each monitored transferred individual data block is ready for a post-processing operation, at least one post-processing operation is performed on the data, and the processed data is transferred to a peripheral device. The method and device may also be adapted for performing an error detection operation on the monitored individual data blocks transferred on the bus, for ascertaining the integrity of the transferred data.
摘要翻译：提供了一种在数据通信系统中的传送进度警报模块和用于优化数据传输负载处理的方法。数据传输负载被划分成各个数据块。该装置和方法同时对不同的单个数据块执行流水线操作，从而优化流水线操作的重叠。该方法包括通过选择预定义的单个数据块大小并且确定用于选择和监视在预定地址区域内的传输地址的传输的密钥来初始化传输。然后，该方法连续地重复以下步骤，直到处理来自数据传输负载的所有监视的单独数据块。首先，输入的单个数据块在外围设备和存储器之间的总线上传送，并且传送进度警报模块用于监视具有确定属于预定地址区域的传输地址的各个数据块。 TPA模块用于确定每个被监控的传送的单独数据块何时准备好进行后处理操作，对数据执行至少一个后处理操作，并且处理的数据被传送到外围设备。所述方法和装置还可以适于对在总线上传送的被监测的各个数据块执行错误检测操作，以确定传送的数据的完整性。

7. 发明申请

US20080109577A1 Method and apparatus for multiplexing multiple protocol handlers on a shared memory bus 失效
标题翻译：用于在共享存储器总线上复用多个协议处理程序的方法和装置
公开(公告)号：US20080109577A1
公开(公告)日：2008-05-08
申请号：US11532936
申请日：2006-09-19
申请人： Michael Joseph Azevedo , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Andrew Dale Walls
IPC分类号： G06F13/00
CPC分类号： G06F13/4243 , H04L47/50 , H04L69/18
摘要： Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.
摘要翻译：协议多路复用器被配置为接收多个通信链路，每个链路以多个通信协议之一操作。协议处理器根据用于特定通信链路的通信协议转换接收的数据并对数据进行帧化。端口复用器将接收到的帧分为数据帧和控制帧。数据帧被复用到单个数据总线上，并且控制帧被复用到单个控制总线上以增加协议多路复用器的性能。

8. 发明授权

US07136400B2 Method and apparatus for multiplexing multiple protocol handlers on a shared memory bus 失效
公开(公告)号：US07136400B2
公开(公告)日：2006-11-14
申请号：US10177222
申请日：2002-06-21
申请人： Michael Joseph Azevedo , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Andrew Dale Walls
IPC分类号： H04J3/04 , H04J3/16 , H04L12/50 , H04L12/28
CPC分类号： G06F13/4243 , H04L47/50 , H04L69/18
摘要： Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.

9. 发明授权

US07787490B2 Method and apparatus for multiplexing multiple protocol handlers on a shared memory bus 失效
标题翻译：用于在共享存储器总线上复用多个协议处理程序的方法和装置
公开(公告)号：US07787490B2
公开(公告)日：2010-08-31
申请号：US11532936
申请日：2006-09-19
申请人： Michael Joseph Azevedo , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Andrew Dale Walls
IPC分类号： H04J3/16 , H04J3/04 , H04L12/50
CPC分类号： G06F13/4243 , H04L47/50 , H04L69/18
摘要： Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.
摘要翻译：协议多路复用器被配置为接收多个通信链路，每个链路以多个通信协议中的一个进行操作。协议处理器根据用于特定通信链路的通信协议转换接收的数据并对数据进行帧化。端口复用器将接收到的帧分为数据帧和控制帧。数据帧被复用到单个数据总线上，并且控制帧被复用到单个控制总线上以增加协议多路复用器的性能。

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