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1. 发明授权

US08048791B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US08048791B2
公开(公告)日：2011-11-01
申请号：US12390907
申请日：2009-02-23
申请人： Michael Hargrove , Richard J. Carter , Ying H Tsang , George Kluth , Kisik Choi
发明人： Michael Hargrove , Richard J. Carter , Ying H Tsang , George Kluth , Kisik Choi
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66651 , H01L21/28167 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L29/1054 , H01L29/513 , H01L29/517
摘要： Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.
摘要翻译：提供了形成包括半导体衬底的半导体器件的方法。根据示例性实施例，一种方法包括形成覆盖在半导体衬底上的沟道层，形成通道封盖层，其具有覆盖沟道层的第一表面，氧化沟道封盖层的第一表面，以及沉积高k电介质覆盖通道封盖层的层。

2. 发明申请

US20130224945A1 METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS 有权
标题翻译：形成具有更换盖的块状FINFET器件的方法，以减少通过泄漏电流的冲击
公开(公告)号：US20130224945A1
公开(公告)日：2013-08-29
申请号：US13408139
申请日：2012-02-29
申请人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans Van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
发明人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans Van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L29/66795
摘要： One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷，以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

3. 发明申请

US20110254092A1 ETSOI CMOS ARCHITECTURE WITH DUAL BACKSIDE STRESSORS 审中-公开
标题翻译： ETSOI CMOS建筑与双背压应力
公开(公告)号：US20110254092A1
公开(公告)日：2011-10-20
申请号：US12759969
申请日：2010-04-14
申请人： Bin Yang , Michael Hargrove
发明人： Bin Yang , Michael Hargrove
IPC分类号： H01L27/092 , H01L21/31
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/12 , H01L29/7849 , H01L29/785 , H01L29/78654
摘要： A semiconductor is formed on an ETSOI layer, the thin Si layer of an ETSOI substrate, with enhanced channel stress. Embodiments include semiconductor devices having dual stress liners on the back surface of the ETSOI layer. An embodiment includes forming an ETSOI substrate comprising an extra thin layer of Si on a backside substrate with an insulating layer, e.g., a BOX, there between, forming a semiconductor device on the Si surface, removing the backside substrate, as by CMP and the insulting layer, as by wet etching, and forming a stress liner on the backside of the remaining Si layer opposite the semiconductor device. The use of stress liners on the backside of the ETSOI layer enhances channel stress without modifying ETSOI semiconductor process flow.
摘要翻译：在ETSOI层，ETSOI衬底的薄Si层上形成半导体，具有增强的沟道应力。实施例包括在ETSOI层的背面上具有双重应力衬垫的半导体器件。一个实施例包括在背面基板上形成包括超薄Si层的ETSOI衬底，其上具有诸如BOX之间的绝缘层（例如BOX），在Si表面上形成半导体器件，通过CMP和绝缘层，如通过湿蚀刻，并且在与半导体器件相对的剩余Si层的背面上形成应力衬垫。在ETSOI层的背面使用应力衬垫增强了通道应力，而不改变ETSOI半导体工艺流程。

4. 发明授权

US07384857B2 Method to fabricate completely isolated silicon regions 失效
标题翻译：制造完全隔离的硅区域的方法
公开(公告)号：US07384857B2
公开(公告)日：2008-06-10
申请号：US11066206
申请日：2005-02-25
申请人： Michael Hargrove
发明人： Michael Hargrove
IPC分类号： H01L21/76
CPC分类号： H01L21/76267
摘要： The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer in areas designated as active regions. The nitrogen modifies the oxidation rate of later implanted oxygen. Regions where the N2 is implanted result in thinner oxide layers. The SIMOX process can begin following the implantation of nitrogen. This results in buried regions of thick and thin oxide layers at fixed depths in the Si substrate. Excess Si on top of the buried thick and thin oxide regions can be polished down to the thick oxide regions to form the active device regions over the thin oxide regions. Thus, the SOI wafer exhibits an STI structure upon completion of the SOI process without a need for additional STI manufacturing steps.
摘要翻译：浅沟槽隔离，STI区域的结构集成到硅绝缘体SOI SOI晶片的SIMOX制造工艺中。在SOI工艺开始之前，将优选的氮（N 2 N 2）种植体施加到指定为活性区域的区域中的硅晶片。氮气修饰后续植入氧气的氧化速率。注入N 2 N的区域导致较薄的氧化物层。 SIMOX工艺可以在植入氮后开始。这导致Si衬底中固定深度处的厚和薄氧化物层的掩埋区域。在掩埋的厚的和薄的氧化物区域的顶部上的过多的Si可以被抛光到厚的氧化物区域，以在薄氧化物区域上形成有源器件区域。因此，在SOI工艺完成时，SOI晶片呈现STI结构，而不需要额外的STI制造步骤。

5. 发明授权

US08809178B2 Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents 有权
标题翻译：用替换栅极形成大量FinFET器件的方法，以减少冲击穿过漏电流
公开(公告)号：US08809178B2
公开(公告)日：2014-08-19
申请号：US13408139
申请日：2012-02-29
申请人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
发明人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L29/66795
摘要： One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷，以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

6. 发明申请

US20110095341A1 METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS 有权
公开(公告)号：US20110095341A1
公开(公告)日：2011-04-28
申请号：US12604281
申请日：2009-10-22
申请人： Rohit Pal , Michael Hargrove , Frank Bin Yang
发明人： Rohit Pal , Michael Hargrove , Frank Bin Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66651 , H01L21/28123 , H01L21/28194 , H01L21/28247 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

7. 发明授权

US07932143B1 Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
标题翻译：用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法
公开(公告)号：US07932143B1
公开(公告)日：2011-04-26
申请号：US12604281
申请日：2009-10-22
申请人： Rohit Pal , Michael Hargrove , Frank Bin Yang
发明人： Rohit Pal , Michael Hargrove , Frank Bin Yang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66651 , H01L21/28123 , H01L21/28194 , H01L21/28247 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.
摘要翻译：提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

8. 发明申请

US20090280627A1 METHOD OF FORMING STEPPED RECESSES FOR EMBEDDED STRAIN ELEMENTS IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成嵌入式应变元件的步进保持的方法
公开(公告)号：US20090280627A1
公开(公告)日：2009-11-12
申请号：US12119384
申请日：2008-05-12
申请人： Rohit Pal , Frank Bin Yang , Michael Hargrove
发明人： Rohit Pal , Frank Bin Yang , Michael Hargrove
IPC分类号： H01L21/322
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/26586 , H01L21/3065 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.
摘要翻译：提供一种制造半导体晶体管器件的方法。制造方法通过形成覆盖诸如硅的半导体材料层的栅极结构开始。然后，围绕栅极结构的侧壁形成间隔物。接下来，非晶化物质的离子以倾斜的角度注入到栅极结构中。在该步骤中，栅极结构和间隔物用作离子注入掩模。离子在半导体材料中形成非晶化区域。此后，非晶化区域被选择性地去除，从而在半导体材料中产生相应的凹槽。此外，凹部被应力诱导半导体材料填充，并且半导体晶体管器件的制造完成。

9. 发明授权

US07598838B2 Variable inductor technique 有权
标题翻译：可变电感技术
公开(公告)号：US07598838B2
公开(公告)日：2009-10-06
申请号：US11073059
申请日：2005-03-04
申请人： Michael Hargrove , Joseph Petrosky
发明人： Michael Hargrove , Joseph Petrosky
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F17/0013 , H01F21/12 , H01F2021/125 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03J2200/35 , H01L2924/00
摘要： An integrated variable inductor is achieved by placing a second closed-loop inductor immediately above or below a primary inductor. The closed-loop configuration of the second inductor may be broken on-chip by several ways, including use of a transistor to selectively short together both ends of the second inductor. If one wishes to alter the inherent inductance characteristics of the primary inductor, the transistor coupling both ends of the second inductor is actuated. Thus, a current applied to the primary inductor induces a current in the second inductor by inductive coupling. The second current in the second inductor then alters the impedance of the primary inductor by mutual inductance. Thus, the inductance value of the primary inductor is altered. To remove the influence of the second inductor on the primary inductor, the closed-loop configuration of the second inductor is broken.
摘要翻译：通过将第二闭环电感器置于主电感器上方或下方来实现集成可变电感器。第二电感器的闭环配置可以通过几种方式在芯片上断开，包括使用晶体管来选择性地将第二电感器的两端短路。如果希望改变初级电感器的固有电感特性，则耦合第二电感器两端的晶体管被致动。因此，施加到初级电感器的电流通过感应耦合在第二电感器中感应出电流。第二电感器中的第二电流然后通过互感改变初级电感器的阻抗。因此，主电感器的电感值被改变。为了消除第二电感器对初级电感器的影响，第二电感器的闭环配置被破坏。

10. 发明授权

US07157926B1 Universal padset concept for high-frequency probing 失效
标题翻译：通用padset概念用于高频探测
公开(公告)号：US07157926B1
公开(公告)日：2007-01-02
申请号：US11221327
申请日：2005-09-06
申请人： Michael Hargrove , Michael Starego
发明人： Michael Hargrove , Michael Starego
IPC分类号： G01R31/26
CPC分类号： G01R35/007 , G01R27/32 , G01R31/2822 , G01R31/2884
摘要： A universal, substrate Padset for de-embedding pad and signal line parasitics has an input pad group including a first input signal pad and a first ground pad; an output pad group including a first output signal pad and a second ground pad; a first input-signal-routing network for routing the first input signal pad to a first input node of a first predetermined test device; a first output-signal-routing network for routing the first output signal pad to a first output node of the first predetermined test device; a second input-signal-routing network for routing the first input signal pad to a second input node of a second predetermined test device; and a second output-signal-routing network for routing the first output signal pad to a second output node of the second predetermined test device. The layout configuration of the first test device is different from the layout configuration of the second test device.
摘要翻译：用于去嵌入焊盘和信号线寄生效应的通用的衬底焊盘具有包括第一输入信号焊盘和第一接地焊盘的输入焊盘组; 包括第一输出信号焊盘和第二接地焊盘的输出焊盘组; 用于将第一输入信号焊盘路由到第一预定测试设备的第一输入节点的第一输入信号路由网络; 第一输出信号路由网络，用于将第一输出信号焊盘路由到第一预定测试设备的第一输出节点; 第二输入信号路由网络，用于将第一输入信号焊盘路由到第二预定测试设备的第二输入节点; 以及第二输出信号路由网络，用于将第一输出信号焊盘路由到第二预定测试设备的第二输出节点。第一测试装置的布局配置与第二测试装置的布局配置不同。

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