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1. 发明授权

US4758950A Method and apparatus for selectively delaying an interrupt of a coprocessor 失效
标题翻译：用于选择性地延迟协处理器的中断的方法和装置
公开(公告)号：US4758950A
公开(公告)日：1988-07-19
申请号：US113343
申请日：1987-04-13
申请人： Michael Cruess , Donald L. Tietjen , Van B. Shahan , Stanley E. Groves
发明人： Michael Cruess , Donald L. Tietjen , Van B. Shahan , Stanley E. Groves
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3881 , G06F9/3861
摘要： A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
摘要翻译：使用标准总线周期将处理器与协处理器进行接口的系统。处理器在其指令流中遇到具有特定操作字格式的指令时，将将操作字后的命令字传送到由操作字中的协处理器标识字段指定的特定协处理器。在解码命令字后，协处理器将响应一组响应原语中的任何一个，这些响应原语定义了协处理器要求处理器在协处理器支持命令时执行的功能。该接口提供了协处理器可能需要的所有功能，包括向适当的异常处理程序选择性向量化。

2. 发明授权

US4780843A Wait mode power reduction system and method for data processor 失效
标题翻译：等待模式功率降低系统和数据处理器的方法
公开(公告)号：US4780843A
公开(公告)日：1988-10-25
申请号：US107899
申请日：1987-10-13
申请人： Donald L. Tietjen
发明人： Donald L. Tietjen
IPC分类号： G06F1/32 , G06F9/30 , G06F1/04
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3287 , Y02B60/1282 , Y02B60/32
摘要： A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.
摘要翻译：一种用于通过根据系统的数据处理部分提供的掉电信号来中止向系统的选定部分提供时钟脉冲的方法和装置，只有当相应的数据处理系统的状态控制信号指示系统的特定部分然后被禁用或以其他方式被禁止中断数据处理部分的操作。

3. 发明授权

US4683534A Method and apparatus for interfacing buses of different sizes 失效
标题翻译：用于连接不同大小的总线的方法和装置
公开(公告)号：US4683534A
公开(公告)日：1987-07-28
申请号：US745477
申请日：1985-06-17
申请人： Donald L. Tietjen , Michael W. Cruess
发明人： Donald L. Tietjen , Michael W. Cruess
IPC分类号： G06F13/40 , G06F3/00
CPC分类号： G06F13/4018
摘要： In a data processing system having a first bus sized to accomodate 2.sup.x units of data and a second bus sized to accomodate 2.sup.y units of data, where x and y are positive integers and y is less than or equal to x, a method and apparatus for determining y from the x least significant bits of a control address, concatenated with a decode control bit, and then decoding the (x-y) most significant bits of the x control address bits to determine which of x data unit transceivers coupled between the first and second buses should be enabled.
摘要翻译：在具有第一总线的数据处理系统中，所述第一总线的大小适于容纳两个数据单元，以及第二总线，其尺寸适于容纳2y个数据单元，其中x和y是正整数，y小于或等于x，从与解码控制位相连接的控制地址的x个最低有效位确定y，然后解码x个控制地址位的（xy）个最高有效位，以确定在第一和第二位之间耦合的x个数据单元收发器中的哪一个应启用总线。

4. 发明授权

US07378993B1 Method and system for transmitting data 有权
标题翻译：发送数据的方法和系统
公开(公告)号：US07378993B1
公开(公告)日：2008-05-27
申请号：US11619932
申请日：2007-01-04
申请人： Colin MacDonald , Alan J. Carlin , Donald L. Tietjen
发明人： Colin MacDonald , Alan J. Carlin , Donald L. Tietjen
IPC分类号： H03M5/00
CPC分类号： H03M5/145
摘要： A method and system for transmitting binary-coded data use partitioning of data words in a plurality of data nibbles. The data nibbles are coded using modified a 1-bit hot coding format that transforms a data nibble in a data segment including a plurality of bit groups. A change in a digital state at a bit position in a more significant bit group is maintained at that bit position in less significant bit groups, and information is transmitted in a form of a transition between digital states. The data segments are transmitted in phases each including one bit group from each data segment. At a receiving terminal, the bit groups are converted back in the binary-coded data words. In one application, the invention is used to reduce power consumption during data transmissions to and from an integrated circuit device.
摘要翻译：用于发送二进制编码数据的方法和系统使用多个数据半字节中的数据字的划分。数据半字节使用修改的1位热编码格式进行编码，该格式转换包括多个位组的数据段中的数据半字节。在较低有效位组中的位位置处，在更高有效位组中的位位置处的数字状态的变化保持在该位位置，并且以数字状态之间的转换的形式发送信息。数据段以各自包括来自每个数据段的一个位组的相位传送。在接收终端，以二进制编码数据字的形式转换位组。在一个应用中，本发明用于降低与集成电路设备之间的数据传输期间的功耗。

5. 发明授权

US5535398A Method and apparatus for providing both power and control by way of an integrated circuit terminal 失效
标题翻译：通过集成电路端子提供电力和控制的方法和装置
公开(公告)号：US5535398A
公开(公告)日：1996-07-09
申请号：US842951
申请日：1992-02-28
申请人： Terry L. Biggs , Donald L. Tietjen , Jesse R. Wilson
发明人： Terry L. Biggs , Donald L. Tietjen , Jesse R. Wilson
IPC分类号： G06F1/08 , G06F1/10 , G06F1/22 , H03K17/693 , G06F1/16
CPC分类号： G06F1/10 , G06F1/08 , G06F1/22 , H03K17/693
摘要： A method and apparatus for providing both power and control by way of an integrated circuit terminal (22). In one form, a clock source (12) supplies a periodic signal to a phase lock loop circuit (32) and to a multiplexer (34). The output of the phase lock loop circuit (32) is a second input to the multiplexer (34). The phase lock loop circuit (32) receives its power from a power and control pin (22). The multiplexer (34) receives its power from a power pin (24). The power and control pin (22) is used as a control input to multiplexer (34). Multiplexer (34) uses the power and control pin (22) to select which input to output as a system clock.
摘要翻译：一种用于通过集成电路端子（22）提供功率和控制的方法和装置。在一种形式中，时钟源（12）将周期信号提供给锁相环电路（32）和复用器（34）。锁相环电路（32）的输出是多路复用器（34）的第二输入。锁相环电路（32）从电源和控制引脚（22）接收其电力。多路复用器（34）从电源引脚（24）接收其电力。电源和控制引脚（22）用作多路复用器（34）的控制输入。多路复用器（34）使用电源和控制引脚（22）选择要作为系统时钟输出的输入。

6. 发明授权

US5961622A System and method for recovering a microprocessor from a locked bus state 失效
标题翻译：从锁定总线状态恢复微处理器的系统和方法
公开(公告)号：US5961622A
公开(公告)日：1999-10-05
申请号：US956966
申请日：1997-10-23
申请人： John Michael Hudson , Donald L. Tietjen , Terry L. Biggs
发明人： John Michael Hudson , Donald L. Tietjen , Terry L. Biggs
IPC分类号： G06F11/00 , G06F11/14 , G06F13/36 , G06F9/46
CPC分类号： G06F11/0757 , G06F11/141
摘要： A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly handled before another consecutive/subsequent watchdog time out occurs, normal software execution will resume. However, if the software watchdog interrupt is not processed and the watchdog timer (38) experiences a second time-out event while the watchdog time-out interrupt (28) is pending, the timer (38) will generate a bus transfer termination signal (30) and set a status bit (270) within a watchdog status register (44). This assertion of termination signal (30) and the setting of the bit (270) allows the microprocessor to determine that a locked bus state exists. In response to the signal (30) and the bit (270), the locked bus (one or more of busses 22, 24, and/or 26) will attempt to recover from the locked bus state.
摘要翻译：使用数据处理系统（10）和方法来从故障操作中恢复CPU。单个定时器（38）用于启用恢复操作。当定时器（38）经历第一次超时事件时，产生软件看门狗中断（28）。如果软件中断（28）在另一个连续/后续的看门狗超时发生之前被正确处理，则正常的软件执行将恢复。但是，如果在看门狗超时中断（28）处于待机状态的情况下未处理软件看门狗中断并且看门狗定时器（38）经历第二个超时事件，则定时器（38）将产生一个总线传输终止信号 30），并在看门狗状态寄存器（44）内设置状态位（270）。终止信号（30）的确定和比特（270）的设置允许微处理器确定存在锁定的总线状态。响应于信号（30）和位（270），锁定总线（一个或多个总线22,24和/或26）将尝试从锁定的总线状态恢复。

7. 发明授权

US5917761A Synchronous memory interface 失效
标题翻译：同步存储器接口
公开(公告)号：US5917761A
公开(公告)日：1999-06-29
申请号：US965640
申请日：1997-11-06
申请人： Donald L. Tietjen , Terry L. Biggs
发明人： Donald L. Tietjen , Terry L. Biggs
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A synchronous memory interface feeds back a buffered (34) clock signal to a microcontroller (20) to simplify and improve output hold time for the memory (38). An output delay circuit (36) in the microcontroller (20) is controlled by the same delayed clock signal as the synchronous memory (38). This delay circuit (36) selectively delays memory signals to the synchronous memory (38) from the microcontroller delay circuit (36). The use of flip-flops (40, 44) in the delay circuit (36) provides a mechanism for scan testing. This enables three different selectable modes of operation of the delay circuit (36) providing flexibility in interfacing in different environments.
摘要翻译：同步存储器接口将缓冲（34）时钟信号反馈给微控制器（20），以简化并提高存储器（38）的输出保持时间。微控制器（20）中的输出延迟电路（36）由与同步存储器（38）相同的延迟时钟信号控制。该延迟电路（36）从微控制器延迟电路（36）选择性地将存储器信号延迟到同步存储器（38）。在延迟电路（36）中使用触发器（40,44）提供扫描测试的机制。这使得延迟电路（36）的三种不同的可选择的操作模式能够提供在不同环境下的接口灵活性。

8. 发明授权

US5872992A System and method for avoiding bus contention on a multiplexed bus by providing a time period subsequent to a read operation 失效
标题翻译：通过提供读取操作之后的时间段来避免多路复用总线上的总线竞争的系统和方法
公开(公告)号：US5872992A
公开(公告)日：1999-02-16
申请号：US519030
申请日：1995-08-24
申请人： Donald L. Tietjen , David M. Menard
发明人： Donald L. Tietjen , David M. Menard
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4213
摘要： A bus interface unit within a processor ensures a delay period after the occurrence of a read operation to avoid bus contention on a multiplexed bus, When there is a requirement for a back-to-back read or write operation subsequent to the read bus cycle on a multiplexed bus it is important to allow devices, such as memory, sufficient time to reset after transmission of data. To avoid the bus contention problem that occurs after a read bus cycle, i.e, prevent a next address on the bus until the bus is in a tri-state condition, one embodiment inserts idle clock cycles subsequent to a read but not subsequent to a write, The present invention avoids bus contention on a multiplexed bus while providing flexibility in interfacing with a variety of memory devices, and providing a flexible processor design.
摘要翻译：处理器内的总线接口单元确保在读操作发生之后的延迟时间，以避免多路复用总线上的总线争用。当需要在读总线周期之后进行背靠背读或写操作时复用的总线重要的是允许诸如存储器的设备在传输数据之后有足够的时间来重置。为了避免在读总线周期之后发生的总线争用问题，即，在总线处于三态条件之前，防止总线上的下一个地址，一个实施例在读取之后插入空闲时钟周期，但不在写入后本发明避免了在多路复用总线上的总线争用，同时提供了与各种存储器件接口的灵活性，并且提供了灵活的处理器设计。

9. 发明授权

US5828827A Data processing system for performing a test function and method therefor 失效
标题翻译：用于执行测试功能的数据处理系统及其方法
公开(公告)号：US5828827A
公开(公告)日：1998-10-27
申请号：US810273
申请日：1997-03-03
申请人： Michael A. Mateja , Tulley M. Peters , Donald L. Tietjen
发明人： Michael A. Mateja , Tulley M. Peters , Donald L. Tietjen
IPC分类号： G01R31/3185 , G06F11/27
CPC分类号： G01R31/318541
摘要： Circuitry is implemented within an integrated circuit ("chip") (101) which is an IEEE 1149.1 compliant device capable of performing JTAG testing (104), such as an EXTEST or CLAMP testing procedure. Upon exiting of either of these procedures, the input/output pins (210) of the chip are placed in a known state, which may be a high impedance state.
摘要翻译：电路在集成电路（“芯片”）（101）中实现，该集成电路是能够执行JTAG测试（104）的IEEE 1149.1兼容设备，例如EXTEST或CLAMP测试程序。在退出这些过程中的任何一个时，芯片的输入/输出引脚（210）被置于已知状态，其可以是高阻抗状态。

10. 发明授权

US5689659A Method and apparatus for bursting operand transfers during dynamic bus sizing 失效
标题翻译：用于在动态总线调整过程中突发操作数传输的方法和装置
公开(公告)号：US5689659A
公开(公告)日：1997-11-18
申请号：US550043
申请日：1995-10-30
申请人： Donald L. Tietjen , Frank C. Galloway , Juan Guillermo Revilla , Nancy G. Woodbridge , David M. Menard , Ronny L. Arnold
发明人： Donald L. Tietjen , Frank C. Galloway , Juan Guillermo Revilla , Nancy G. Woodbridge , David M. Menard , Ronny L. Arnold
IPC分类号： G06F13/28 , G06F13/40 , G06F13/00
CPC分类号： G06F13/28 , G06F13/4018
摘要： A data processing system (10) having a bus controller (5) that uses a communication bus (22) which adapts to various system resources (7) and is capable of burst transfers. In one embodiment, the processor core (2) and system resources (7) supply control signals supplying required parameters of the next transfer. The bus controller is capable of transferring operands and/or instructions in incremental bursts from these system resources. Each transfer data burst has an associated unique access address where successive bytes of data are associated with sequential addresses and the burst increment equals the data port size. The burst capability is dependent on the ability of system resource (7) to burst data and can be inhibited with a transfer burst inhibit signal. The length of the desired data is controlled by a sizing signal from the core (2) or from cache and the increment size is supplied by the resource (7).
摘要翻译：一种具有总线控制器（5）的数据处理系统（10），该总线控制器（5）使用适应各种系统资源（7）并且能够进行突发传输的通信总线（22）。在一个实施例中，处理器核心（2）和系统资源（7）提供提供下一个传输的所需参数的控制信号。总线控制器能够以这些系统资源的增量突发传送操作数和/或指令。每个传输数据脉冲串具有相关联的唯一访问地址，其中连续的数据字节与顺序地址相关联，并且突发增量等于数据端口大小。突发能力取决于系统资源（7）突发数据的能力，并且可以用传输突发禁止信号来禁止。所需数据的长度由来自核心（2）或高速缓存的大小调整信号控制，增量大小由资源（7）提供。

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