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1. 发明授权

US5535398A Method and apparatus for providing both power and control by way of an integrated circuit terminal 失效
标题翻译：通过集成电路端子提供电力和控制的方法和装置
公开(公告)号：US5535398A
公开(公告)日：1996-07-09
申请号：US842951
申请日：1992-02-28
申请人： Terry L. Biggs , Donald L. Tietjen , Jesse R. Wilson
发明人： Terry L. Biggs , Donald L. Tietjen , Jesse R. Wilson
IPC分类号： G06F1/08 , G06F1/10 , G06F1/22 , H03K17/693 , G06F1/16
CPC分类号： G06F1/10 , G06F1/08 , G06F1/22 , H03K17/693
摘要： A method and apparatus for providing both power and control by way of an integrated circuit terminal (22). In one form, a clock source (12) supplies a periodic signal to a phase lock loop circuit (32) and to a multiplexer (34). The output of the phase lock loop circuit (32) is a second input to the multiplexer (34). The phase lock loop circuit (32) receives its power from a power and control pin (22). The multiplexer (34) receives its power from a power pin (24). The power and control pin (22) is used as a control input to multiplexer (34). Multiplexer (34) uses the power and control pin (22) to select which input to output as a system clock.
摘要翻译：一种用于通过集成电路端子（22）提供功率和控制的方法和装置。在一种形式中，时钟源（12）将周期信号提供给锁相环电路（32）和复用器（34）。锁相环电路（32）的输出是多路复用器（34）的第二输入。锁相环电路（32）从电源和控制引脚（22）接收其电力。多路复用器（34）从电源引脚（24）接收其电力。电源和控制引脚（22）用作多路复用器（34）的控制输入。多路复用器（34）使用电源和控制引脚（22）选择要作为系统时钟输出的输入。

2. 发明授权

US5961622A System and method for recovering a microprocessor from a locked bus state 失效
标题翻译：从锁定总线状态恢复微处理器的系统和方法
公开(公告)号：US5961622A
公开(公告)日：1999-10-05
申请号：US956966
申请日：1997-10-23
申请人： John Michael Hudson , Donald L. Tietjen , Terry L. Biggs
发明人： John Michael Hudson , Donald L. Tietjen , Terry L. Biggs
IPC分类号： G06F11/00 , G06F11/14 , G06F13/36 , G06F9/46
CPC分类号： G06F11/0757 , G06F11/141
摘要： A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly handled before another consecutive/subsequent watchdog time out occurs, normal software execution will resume. However, if the software watchdog interrupt is not processed and the watchdog timer (38) experiences a second time-out event while the watchdog time-out interrupt (28) is pending, the timer (38) will generate a bus transfer termination signal (30) and set a status bit (270) within a watchdog status register (44). This assertion of termination signal (30) and the setting of the bit (270) allows the microprocessor to determine that a locked bus state exists. In response to the signal (30) and the bit (270), the locked bus (one or more of busses 22, 24, and/or 26) will attempt to recover from the locked bus state.
摘要翻译：使用数据处理系统（10）和方法来从故障操作中恢复CPU。单个定时器（38）用于启用恢复操作。当定时器（38）经历第一次超时事件时，产生软件看门狗中断（28）。如果软件中断（28）在另一个连续/后续的看门狗超时发生之前被正确处理，则正常的软件执行将恢复。但是，如果在看门狗超时中断（28）处于待机状态的情况下未处理软件看门狗中断并且看门狗定时器（38）经历第二个超时事件，则定时器（38）将产生一个总线传输终止信号 30），并在看门狗状态寄存器（44）内设置状态位（270）。终止信号（30）的确定和比特（270）的设置允许微处理器确定存在锁定的总线状态。响应于信号（30）和位（270），锁定总线（一个或多个总线22,24和/或26）将尝试从锁定的总线状态恢复。

3. 发明授权

US5917761A Synchronous memory interface 失效
标题翻译：同步存储器接口
公开(公告)号：US5917761A
公开(公告)日：1999-06-29
申请号：US965640
申请日：1997-11-06
申请人： Donald L. Tietjen , Terry L. Biggs
发明人： Donald L. Tietjen , Terry L. Biggs
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A synchronous memory interface feeds back a buffered (34) clock signal to a microcontroller (20) to simplify and improve output hold time for the memory (38). An output delay circuit (36) in the microcontroller (20) is controlled by the same delayed clock signal as the synchronous memory (38). This delay circuit (36) selectively delays memory signals to the synchronous memory (38) from the microcontroller delay circuit (36). The use of flip-flops (40, 44) in the delay circuit (36) provides a mechanism for scan testing. This enables three different selectable modes of operation of the delay circuit (36) providing flexibility in interfacing in different environments.
摘要翻译：同步存储器接口将缓冲（34）时钟信号反馈给微控制器（20），以简化并提高存储器（38）的输出保持时间。微控制器（20）中的输出延迟电路（36）由与同步存储器（38）相同的延迟时钟信号控制。该延迟电路（36）从微控制器延迟电路（36）选择性地将存储器信号延迟到同步存储器（38）。在延迟电路（36）中使用触发器（40,44）提供扫描测试的机制。这使得延迟电路（36）的三种不同的可选择的操作模式能够提供在不同环境下的接口灵活性。

4. 发明授权

US5410669A Data processor having a cache memory capable of being used as a linear ram bank 失效
标题翻译：数据处理器具有能够用作线性压头库的高速缓冲存储器
公开(公告)号：US5410669A
公开(公告)日：1995-04-25
申请号：US043065
申请日：1993-04-05
申请人： Terry L. Biggs , Antonio A. Lagana
发明人： Terry L. Biggs , Antonio A. Lagana
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0864 , G06F12/0802 , G06F2212/2515
摘要： A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache set or as a static random access memory (SRAM) bank. Based upon the configuration of the set, the tag store array (58) is used for storage of actual data, in the SRAM mode, or for storage of a set of tag entries in the cache mode. A module configuration register (40) specifies the mode of each set/bank. A set of base address registers (41-44) define the upper bits of a base address of SRAM banks. In SRAM mode, comparison logic (66) compares a tag field of the requested address (50) to the base address to determine an access hit. The least significant bit of the address, tag field is used to select either the tag store array (58) or the line array (60) for the requested address data read or write.
摘要翻译：一种具有包括多个高速缓存组的双重目的存储器（14）的数据处理系统（10）。每个缓存组可以单独配置为高速缓存集或静态随机存取存储器（SRAM）组。基于集合的配置，标签存储阵列（58）用于以SRAM模式存储实际数据，或用于存储高速缓存模式中的一组标签条目。模块配置寄存器（40）指定每个组/组的模式。一组基址寄存器（41-44）定义了SRAM存储体的基址的高位。在SRAM模式中，比较逻辑（66）将请求的地址（50）的标签字段与基地址进行比较，以确定访问命中。地址的最低有效位标签字段用于为所请求的地址数据读取或写入选择标签存储阵列（58）或线阵列（60）。

5. 发明授权

US06226724B1 Memory controller and method for generating commands to a memory 失效
标题翻译：用于向存储器生成命令的存储器控制器和方法
公开(公告)号：US06226724B1
公开(公告)日：2001-05-01
申请号：US08929128
申请日：1997-09-03
申请人： Terry L. Biggs
发明人： Terry L. Biggs
IPC分类号： G06F1200
CPC分类号： G06F13/1631
摘要： A memory controller (42) controls accesses to a command-based memory device (43) such as a synchronous DRAM. The memory controller (42) uses an address comparator (45) for both base address matching and command generation. When the memory controller (42) detects an access to the memory device (43) and a control register bit is set, a state machine (56) causes the command to be written to the memory device (43). The memory controller (42) thus allows the memory device (43) to be accessed with little additional circuitry, and to be connected to higher order address bits to speed the access. Since the commands are detected by accesses to the same memory locations as reads and writes, the memory controller (42) avoids creating “holes” in the memory map.
摘要翻译：存储器控制器（42）控制对诸如同步DRAM的基于命令的存储器件（43）的访问。存储器控制器（42）使用地址比较器（45）用于基地址匹配和命令生成两者。当存储器控制器（42）检测到对存储器件（43）的访问并且设置了控制寄存器位时，状态机（56）使命令被写入存储器件（43）。因此，存储器控制器（42）允许以少量额外的电路访问存储器件（43），并且连接到更高位地址位以加速访问。由于通过访问与读取和写入相同的存储器位置来检测命令，存储器控制器（42）避免在存储器映射中产生“空洞”。

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