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1. 发明授权

US5075846A Memory access serialization as an MMU page attribute 失效
标题翻译：内存访问序列化为MMU页面属性
公开(公告)号：US5075846A
公开(公告)日：1991-12-24
申请号：US414335
申请日：1989-09-29
申请人： Russell A. Reininger , William B. Ledbetter, Jr. , Robin W. Edenfield , Van B. Shahan , Ralph C. McGarity , Eric E. Quintana
发明人： Russell A. Reininger , William B. Ledbetter, Jr. , Robin W. Edenfield , Van B. Shahan , Ralph C. McGarity , Eric E. Quintana
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0877 , G06F9/3834
摘要： A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.
摘要翻译：提供了具有基于页面的序列化属性的数据处理器。一组页面描述符和透明的翻译寄存器将序列化属性编码为高速缓存模式。数据处理器是一个流水线机器，具有至少两个功能单元，它们彼此独立地工作。功能单元向访问控制器发出访问存储在外部存储器中的信息的请求。访问控制器用作仲裁机制，并且根据功能单元的请求的发布顺序来授予功能单元的请求。当存储器访问在页面描述符中被标记为序列化时，访问控制器推迟序列化访问，直到指令序列中所有待处理的存储器访问完成为止。所有待处理的请求随后以预定的顺序完成，而与功能单元的请求的发布顺序无关，并且完成所有适当的异常处理。然后完成推迟的序列化访问。

2. 发明授权

US5185694A Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies 失效
标题翻译：数据处理系统使用块数据输入的块移动指令数据块的宽度范围
公开(公告)号：US5185694A
公开(公告)日：1993-02-09
申请号：US371343
申请日：1989-06-26
申请人： Robin W. Edenfield , Ralph McGarity , Russell Reininger , William B. Ledbetter, Jr. , Van B. Shahan
发明人： Robin W. Edenfield , Ralph McGarity , Russell Reininger , William B. Ledbetter, Jr. , Van B. Shahan
IPC分类号： G06F12/08 , G06F9/315 , G06F13/28
CPC分类号： G06F9/30032
摘要： A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus for both reads and writes. The instruction allows the programmer to fully utilize the maximum bus bandwidth of the system bus for memory to memory transfers of data (e.g. DMA, block moves, memory page initialization) and transfers of instructions/data to detached coprocessors.

3. 发明授权

US4777613A Floating point numeric data processor 失效
标题翻译：浮点数字数据处理器
公开(公告)号：US4777613A
公开(公告)日：1988-10-11
申请号：US847064
申请日：1986-04-01
申请人： Van B. Shahan , Paul E. Harvey , Clayton D. Huntsman , Ashok H. Someshway
发明人： Van B. Shahan , Paul E. Harvey , Clayton D. Huntsman , Ashok H. Someshway
IPC分类号： G06F7/544 , G06F7/57 , G06F7/38
CPC分类号： G06F7/483 , G06F7/5446 , G06F7/4991 , G06F7/49947
摘要： A numeric data processor having an execution unit adapted to efficiently execute the complete set of floating point operations recommended by the IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std. 754-1985, in full compliance therewith. The numeric data processor is also adapted to evaluate a large set of transcendental functions, including trigonometric, logarithmic and exponential, consistent with the IEEE Standard, without requiring a "software envelope." In the processor, special hybrid forms of Volder's CORDIC digital approximator and Meggitt's digital approximator are implemented in a manner so as to require minimal additions or modifications to the form of the execution unit which is otherwise required just to execute the standard floating point operations.
摘要翻译：一种具有执行单元的数字数据处理器，其适于有效地执行IEEE标准的二进制浮点算术推荐的完整的一组浮点运算，ANSI / IEEE标准。 754-1985，完全符合。数字数据处理器还适用于评估符合IEEE标准的大量超越函数，包括三角，对数和指数，而不需要“软件包络”。在处理器中，Volder的CORDIC数字近似器和Meggitt的数字近似器的特殊混合形式以一种方式实现，以便要求对执行单元的形式进行最小的补充或修改，否则这仅需要执行标准浮点运算。

4. 发明授权

US4758950A Method and apparatus for selectively delaying an interrupt of a coprocessor 失效
标题翻译：用于选择性地延迟协处理器的中断的方法和装置
公开(公告)号：US4758950A
公开(公告)日：1988-07-19
申请号：US113343
申请日：1987-04-13
申请人： Michael Cruess , Donald L. Tietjen , Van B. Shahan , Stanley E. Groves
发明人： Michael Cruess , Donald L. Tietjen , Van B. Shahan , Stanley E. Groves
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3881 , G06F9/3861
摘要： A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
摘要翻译：使用标准总线周期将处理器与协处理器进行接口的系统。处理器在其指令流中遇到具有特定操作字格式的指令时，将将操作字后的命令字传送到由操作字中的协处理器标识字段指定的特定协处理器。在解码命令字后，协处理器将响应一组响应原语中的任何一个，这些响应原语定义了协处理器要求处理器在协处理器支持命令时执行的功能。该接口提供了协处理器可能需要的所有功能，包括向适当的异常处理程序选择性向量化。

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