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1. 发明授权

US08522000B2 Trap handler architecture for a parallel processing unit 有权
标题翻译：并行处理单元的陷阱处理器架构
公开(公告)号：US08522000B2
公开(公告)日：2013-08-27
申请号：US12569831
申请日：2009-09-29
申请人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
发明人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
IPC分类号： G06F9/00
CPC分类号： G06F9/327 , G06F9/3851 , G06F9/3861
摘要： A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.
摘要翻译：陷阱处理器架构被并入到诸如GPU的并行处理子系统中。陷阱处理器架构通过强加与流式多处理器相关联的所有线程组都在其各自的代码段内执行或全部在陷阱处理程序代码段内执行的属性来最小化并发执行线程的设计复杂性和验证工作。

2. 发明申请

US20110078427A1 TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT 有权
标题翻译：并行处理单元的TRAP操作架构
公开(公告)号：US20110078427A1
公开(公告)日：2011-03-31
申请号：US12569831
申请日：2009-09-29
申请人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
发明人： Michael C. Shebanow , Jack Choquette , Brett W. Coon , Steven J. Heinrich , Aravind Kalaiah , John R. Nickolls , Daniel Salinas , Ming Y. Siu , Tommy Thorn , Nicholas Wang
IPC分类号： G06F9/38
CPC分类号： G06F9/327 , G06F9/3851 , G06F9/3861
摘要： A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.
摘要翻译：陷阱处理器架构被并入到诸如GPU的并行处理子系统中。陷阱处理器架构通过强加与流式多处理器相关联的所有线程组都在其各自的代码段内执行或全部在陷阱处理程序代码段内执行的属性来最小化并发执行线程的设计复杂性和验证工作。

3. 发明授权

US09361114B1 Instruction based interrupt masking for managing interrupts in a computer environment 有权
标题翻译：基于指令的中断屏蔽，用于管理计算机环境中的中断
公开(公告)号：US09361114B1
公开(公告)日：2016-06-07
申请号：US11296651
申请日：2005-12-06
申请人： Gil Tene , Scott Sellers , Jack Choquette , Michael A. Wolf
发明人： Gil Tene , Scott Sellers , Jack Choquette , Michael A. Wolf
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/38 , G06F9/48
CPC分类号： G06F9/3861 , G06F9/327 , G06F9/4812
摘要： Managing interrupts in a computing environment includes executing an instruction, deriving an interrupt mask value based at least in part on the instruction being executed, performing a masking operation involving the interrupt mask value and at least one pending interrupt to determine whether a pending interrupt is allowable, and in the event that the pending interrupt is allowable, performing the interrupt.
摘要翻译：管理计算环境中的中断包括执行指令，至少部分地基于所执行的指令来导出中断屏蔽值，执行涉及中断屏蔽值的屏蔽操作和至少一个未决中断，以确定是否允许未决中断，并且在允许待处理中断的情况下，执行中断。

4. 发明授权

US07552302B1 Ordering operation 有权
标题翻译：订货操作
公开(公告)号：US07552302B1
公开(公告)日：2009-06-23
申请号：US11227448
申请日：2005-09-14
申请人： Gil Tene , Kevin Normoyle , Jack Choquette , David Kruckernyer , Cliff N. Click, Jr.
发明人： Gil Tene , Kevin Normoyle , Jack Choquette , David Kruckernyer , Cliff N. Click, Jr.
IPC分类号： G06F12/02
CPC分类号： G06F8/315 , G06F9/3001 , G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/345 , G06F9/355 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/461
摘要： Executing an ordering operation is disclosed. A store operation associated with storing a value into a portion of a memory is initiated. An ordering operation to ensure that the store operation, but not necessarily all store operations, are completed is executed.
摘要翻译：公开了执行排序操作。启动与存储器的一部分中存储值相关联的存储操作。执行订购操作，以确保完成存储操作，但不一定全部存储操作。

5. 发明授权

US06594753B2 Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units 失效
公开(公告)号：US06594753B2
公开(公告)日：2003-07-15
申请号：US09519524
申请日：2000-03-06
申请人： Jack Choquette , Norman K. Yeung
发明人： Jack Choquette , Norman K. Yeung
IPC分类号： G06F930
CPC分类号： G06F9/3891 , G06F9/3836 , G06F9/3885
摘要： A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.

6. 发明授权

US09606808B2 Method and system for resolving thread divergences 有权
公开(公告)号：US09606808B2
公开(公告)日：2017-03-28
申请号：US13348544
申请日：2012-01-11
申请人： Jack Choquette , Xiaogang Qiu , Jeff Tuckey , Michael (Ming Yiu) Siu , Robert J. Stoll , Olivier Giroux
发明人： Jack Choquette , Xiaogang Qiu , Jeff Tuckey , Michael (Ming Yiu) Siu , Robert J. Stoll , Olivier Giroux
IPC分类号： G06F9/38
CPC分类号： G06F9/3887 , G06F9/3851
摘要： A computing device detects divergences between threads in a thread group executing on a parallel processing unit. The computing device includes an address divergence unit that identifies a subset of non-divergent threads included in the thread group. The address divergence unit stores instructions related to the subset of non-divergent threads in a multi-issue queue. The address divergence unit causes the instructions related to the subset of non-divergent threads to be retrieved from the multi-issue queue when the parallel processing unit is available. The address divergence unit causes the subset of non-divergent threads to be issued for execution on the parallel processing unit. The address divergence unit repeats the identifying, storing, and causing steps for the remaining threads in the thread group that are not included in the subset of non-divergent threads.

7. 发明授权

US06708282B1 Method and system for initiating computation upon unordered receipt of data 有权
标题翻译：用于在无序接收数据时启动计算的方法和系统
公开(公告)号：US06708282B1
公开(公告)日：2004-03-16
申请号：US09654759
申请日：2000-09-05
申请人： Dominic Paul McCarthy , Jack Choquette
发明人： Dominic Paul McCarthy , Jack Choquette
IPC分类号： G06F1342
CPC分类号： G06F9/52
摘要： In complex systems, the arrival of data to a computation component is difficult to predict. A method of synchronizing the initiation of computation with the reception of its input data is disclosed. The method allows the input data and computation initiation commands to arrive in any order. The method is dynamically adjustable allowing for varying numbers of data inputs.
摘要翻译：在复杂的系统中，难以预测数据到计算组件的到来。公开了一种使计算开始与其输入数据的接收同步的方法。该方法允许输入数据和计算启动命令以任何顺序到达。该方法可动态调整，允许不同数量的数据输入。

8. 发明申请

US20100153689A1 Processor instruction used to determine whether to perform a memory-related trap 有权
标题翻译：处理器指令用于确定是否执行内存相关的陷阱
公开(公告)号：US20100153689A1
公开(公告)日：2010-06-17
申请号：US12658669
申请日：2010-02-12
申请人： Jack Choquette , Gil Tene , Michael A. Wolf
发明人： Jack Choquette , Gil Tene , Michael A. Wolf
IPC分类号： G06F9/38 , G06F12/10
CPC分类号： G06F12/0253 , G06F9/3004 , G06F9/3861 , G06F11/2236
摘要： Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.
摘要翻译：指令执行包括获取包括识别指令的一个或多个比特的第一组的指令，以及与第一地址值相关联的一个或多个比特的第二组。它还包括执行指令以确定是否执行陷阱，其中执行指令包括从多个测试中选择至少一个用于确定是否执行陷阱并进行至少一个测试的测试。在确定是否执行陷阱时使用第二组一个或多个比特; 并且所述多个测试包括矩阵测试，所述矩阵测试确定由所述第一地址值指示的存储的数据值是否从多个管理存储器类型中的一个转移到所述多个管理存储器类型中的另一个，并产生陷阱在数据值被确定为从多个托管存储器类型之一转移到多个托管存储器类型中的另一个的情况下，其中矩阵测试基于与垃圾收集相关联的矩阵和位于使用一个或多个比特的第一组中的至少一些以及一个或多个比特的第二组中的至少一些。

9. 发明授权

US6035388A Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units 失效
公开(公告)号：US6035388A
公开(公告)日：2000-03-07
申请号：US883147
申请日：1997-06-27
申请人： Jack Choquette , Norman K. Yeung
发明人： Jack Choquette , Norman K. Yeung
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3891 , G06F9/3836 , G06F9/3885
摘要： A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.

10. 发明授权

US07689782B1 Processor instruction used to determine whether to perform a memory-related trap 有权
标题翻译：处理器指令用于确定是否执行内存相关的陷阱
公开(公告)号：US07689782B1
公开(公告)日：2010-03-30
申请号：US11296195
申请日：2005-12-06
申请人： Jack Choquette , Gil Tene , Michael A. Wolf
发明人： Jack Choquette , Gil Tene , Michael A. Wolf
IPC分类号： G06F13/00
CPC分类号： G06F12/0253 , G06F9/30003
摘要： An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.
摘要翻译：公开了处理器在确定是否执行陷阱时使用的指令。所述指令包括识别所述指令的一个或多个比特的第一组以及与所述确定中使用的第一地址值相关联的一个或多个比特的第二组。该确定不包括执行使用第一地址值来确定存储器访问的存储器位置的存储器访问。该确定至少部分地基于以下中的多于一个：包含在第一地址值中的一组或多个标记位的组，至少部分地使用第一地址值的一个或多个位的矩阵项，与第一地址值相关联的翻译后备缓冲器条目，第一地址值是否与堆栈分配的存储器相关联，以及第一地址值是否包括空值。

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