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1. 发明授权

US09606808B2 Method and system for resolving thread divergences 有权
公开(公告)号：US09606808B2
公开(公告)日：2017-03-28
申请号：US13348544
申请日：2012-01-11
申请人： Jack Choquette , Xiaogang Qiu , Jeff Tuckey , Michael (Ming Yiu) Siu , Robert J. Stoll , Olivier Giroux
发明人： Jack Choquette , Xiaogang Qiu , Jeff Tuckey , Michael (Ming Yiu) Siu , Robert J. Stoll , Olivier Giroux
IPC分类号： G06F9/38
CPC分类号： G06F9/3887 , G06F9/3851
摘要： A computing device detects divergences between threads in a thread group executing on a parallel processing unit. The computing device includes an address divergence unit that identifies a subset of non-divergent threads included in the thread group. The address divergence unit stores instructions related to the subset of non-divergent threads in a multi-issue queue. The address divergence unit causes the instructions related to the subset of non-divergent threads to be retrieved from the multi-issue queue when the parallel processing unit is available. The address divergence unit causes the subset of non-divergent threads to be issued for execution on the parallel processing unit. The address divergence unit repeats the identifying, storing, and causing steps for the remaining threads in the thread group that are not included in the subset of non-divergent threads.

2. 发明授权

US08732713B2 Thread group scheduler for computing on a parallel thread processor 有权
标题翻译：线程组调度程序，用于在并行线程处理器上进行计算
公开(公告)号：US08732713B2
公开(公告)日：2014-05-20
申请号：US13247819
申请日：2011-09-28
申请人： Brett W. Coon , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
发明人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value.
摘要翻译：并行线程处理器执行属于多个协作线程数组（CTA）的线程组。在并行线程处理器的每个周期，指令调度器在随后的周期中选择要发行的线程组以执行。指令调度器通过（i）识别可用线程组的池，（ii）识别具有最大资历值的CTA来选择要执行的线程组，以及（iii）选择具有最大信用值的线程组从具有最高资历价值的CTA内。

3. 发明申请

US20130166881A1 METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS USING PRE-DECODE DATA 有权
标题翻译：使用预编码数据调度指令的方法和装置
公开(公告)号：US20130166881A1
公开(公告)日：2013-06-27
申请号：US13333879
申请日：2011-12-21
申请人： Jack Hilaire CHOQUETTE , Robert J. Stoll , Olivier Giroux
发明人： Jack Hilaire CHOQUETTE , Robert J. Stoll , Olivier Giroux
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/382
摘要： Systems and methods for scheduling instructions using pre-decode data corresponding to each instruction. In one embodiment, a multi-core processor includes a scheduling unit in each core for selecting instructions from two or more threads each scheduling cycle for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The pre-decode data is determined by a compiler and is extracted by the scheduling unit during runtime and used to control selection of threads for execution. The pre-decode data may specify a number of scheduling cycles to wait before scheduling the instruction. The pre-decode data may also specify a scheduling priority for the instruction. Once the scheduling unit selects an instruction to issue for execution, a decode unit fully decodes the instruction.
摘要翻译：用于使用对应于每个指令的预解码数据调度指令的系统和方法。在一个实施例中，多核处理器包括每个核心中的调度单元，用于从两个或更多个线程中选择用于在该特定核心上执行的调度周期的指令。由于线程被安排在核心上执行，所以来自线程的指令被取入到缓冲器中而不被解码。预解码数据由编译器确定，并且在运行时由调度单元提取并用于控制用于执行的线程的选择。预解码数据可以指定在调度指令之前等待的多个调度周期。预解码数据还可以指定该指令的调度优先级。一旦调度单元选择要执行的指令，则解码单元完全解码该指令。

4. 发明授权

US09830158B2 Speculative execution and rollback 有权
公开(公告)号：US09830158B2
公开(公告)日：2017-11-28
申请号：US13289643
申请日：2011-11-04
申请人： Jack Hilaire Choquette , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
发明人： Jack Hilaire Choquette , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3887
摘要： One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of other instructions. A scheduler circuit issues instructions for execution assuming that, several cycles later, when the instructions reach multithreaded execution units, that dependencies between the instructions will be resolved, resources will be available, operand data will be available, and other conditions will not prevent execution of the instructions. When a rollback condition exists at the point of execution for an instruction for a particular thread group, the instruction is not dispatched to the multithreaded execution units. However, other instructions issued by the scheduler circuit for execution by different thread groups, and for which a rollback condition does not exist, are executed by the multithreaded execution units. The instruction incurring the rollback condition is reissued after the rollback condition no longer exists.

5. 发明授权

US09189242B2 Credit-based streaming multiprocessor warp scheduling 有权
标题翻译：基于信用流的多处理器扭曲调度
公开(公告)号：US09189242B2
公开(公告)日：2015-11-17
申请号：US12885299
申请日：2010-09-17
申请人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
发明人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
IPC分类号： G06F9/50 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution.
摘要翻译：本发明的一个实施例提出了一种用于确保高速缓存访问指令被调度用于在多线程系统中执行以提高高速缓存位置和系统性能的技术。可以使用基于信用的技术来对组中的每个翘曲的指令调度来控制指令，使得一组经线被均匀地处理。对每个经纱计算信用额度，并且信用额度有助于每个经线的权重。权重用于选择要执行的经纱的说明。

6. 发明申请

US20130117541A1 SPECULATIVE EXECUTION AND ROLLBACK 有权
标题翻译：统一执行和滚动
公开(公告)号：US20130117541A1
公开(公告)日：2013-05-09
申请号：US13289643
申请日：2011-11-04
申请人： Jack Hilaire CHOQUETTE , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
发明人： Jack Hilaire CHOQUETTE , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3887
摘要： One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of other instructions. A scheduler circuit issues instructions for execution assuming that, several cycles later, when the instructions reach multithreaded execution units, that dependencies between the instructions will be resolved, resources will be available, operand data will be available, and other conditions will not prevent execution of the instructions. When a rollback condition exists at the point of execution for an instruction for a particular thread group, the instruction is not dispatched to the multithreaded execution units. However, other instructions issued by the scheduler circuit for execution by different thread groups, and for which a rollback condition does not exist, are executed by the multithreaded execution units. The instruction incurring the rollback condition is reissued after the rollback condition no longer exists.
摘要翻译：本发明的一个实施例提出了一种用于推测发出指令以允许处理流水线在其他指令的回滚期间继续处理一些指令的技术。调度器电路发出执行指令，假设几个周期后，当指令到达多线程执行单元时，指令之间的相关性将被解决，资源将可用，操作数数据将可用，而其他条件将不会阻止执行说明。当在特定线程组的指令的执行点处存在回滚条件时，指令不会分派给多线程执行单元。然而，由多线程执行单元执行由调度器电路发出的用于由不同线程组执行并且不存在回滚条件的其他指令。在回滚条件不再存在之后，重新发出导致回滚条件的指令。

7. 发明授权

US07692659B1 Color-compression using automatic reduction of multi-sampled pixels 有权
标题翻译：使用自动缩小多采样像素进行色彩压缩
公开(公告)号：US07692659B1
公开(公告)日：2010-04-06
申请号：US11557076
申请日：2006-11-06
申请人： Steven E Molnar , Daniel P. Wilde , Mark J. French , Robert J. Stoll
发明人： Steven E Molnar , Daniel P. Wilde , Mark J. French , Robert J. Stoll
IPC分类号： G06T15/60 , G09G5/36 , G06T9/00 , G09G5/02 , G06K9/00 , G06K9/40 , G06K9/54
CPC分类号： G06T15/005 , G06T9/00
摘要： One embodiment of the present invention sets forth a technique for improving graphics rendering efficiency by processing pixels in a compressed format whenever possible within a multi-sampling graphics pipeline. Each geometric primitive is rasterized into fragments, corresponding to screen space pixels covered at least partially by the geometric primitive. Fragment coverage represents the pixel area covered by the geometric primitive and determines the weighted contribution of a fragment color to the corresponding screen space pixel. Samples associated with a given fragment are called sibling samples and have the same color value. The property of sibling samples having the same color value is exploited to compress and process multiple samples, thereby reducing the size of the associated logic and the amount of data written to and read from the frame buffer.
摘要翻译：本发明的一个实施例提出了一种通过在多采样图形流水线内尽可能处理压缩格式的像素来提高图形渲染效率的技术。每个几何图元被光栅化成片段，对应于至少部分地被几何原始图案覆盖的屏幕空间像素。片段覆盖表示由几何图元覆盖的像素区域，并确定片段颜色对相应屏幕空间像素的加权贡献。与给定片段相关联的样本称为兄弟样本，并具有相同的颜色值。利用具有相同颜色值的兄弟样本的属性来压缩和处理多个样本，从而减小相关逻辑的大小以及写入和从帧缓冲器读取的数据量。

8. 发明授权

US08233004B1 Color-compression using automatic reduction of multi-sampled pixels 有权
标题翻译：使用自动缩小多采样像素进行色彩压缩
公开(公告)号：US08233004B1
公开(公告)日：2012-07-31
申请号：US11557068
申请日：2006-11-06
申请人： Steven E Molnar , Daniel P. Wilde , Mark J. French , Robert J. Stoll
发明人： Steven E Molnar , Daniel P. Wilde , Mark J. French , Robert J. Stoll
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T9/00 , G06T11/40 , G09G5/363 , G09G2340/02
摘要： One embodiment of the present invention sets forth a technique for improving graphics rendering efficiency by processing pixels in a compressed format whenever possible within a multi-sampling graphics pipeline. Each geometric primitive is rasterized into fragments, corresponding to screen space pixels covered at least partially by the geometric primitive. Fragment coverage represents the pixel area covered by the geometric primitive and determines the weighted contribution of a fragment color to the corresponding screen space pixel. Samples associated with a given fragment are called sibling samples and have the same color value. The property of sibling samples having the same color value is exploited to compress and process multiple samples, thereby reducing the size of the associated logic and the amount of data written to and read from the frame buffer.
摘要翻译：本发明的一个实施例提出了一种通过在多采样图形流水线内尽可能处理压缩格式的像素来提高图形渲染效率的技术。每个几何图元被光栅化成片段，对应于至少部分地被几何原始图案覆盖的屏幕空间像素。片段覆盖表示由几何图元覆盖的像素区域，并确定片段颜色对相应屏幕空间像素的加权贡献。与给定片段相关联的样本称为兄弟样本，并具有相同的颜色值。利用具有相同颜色值的兄弟样本的属性来压缩和处理多个样本，从而减小相关逻辑的大小以及写入和从帧缓冲器读取的数据量。

9. 发明授权

US08125489B1 Processing pipeline with latency bypass 有权
标题翻译：处理具有延迟旁路的流水线
公开(公告)号：US08125489B1
公开(公告)日：2012-02-28
申请号：US11532760
申请日：2006-09-18
申请人： Peter B. Holmqvist , Robert J. Stoll , John A. Schachte
发明人： Peter B. Holmqvist , Robert J. Stoll , John A. Schachte
IPC分类号： G06F13/14
CPC分类号： G06F9/3826 , G06F9/3836 , G06F9/3867 , G09G2360/121
摘要： A processing pipeline employs one or more bypass caches to allow a transaction that is dependent on the results of a prior transaction to be processed before the prior transaction has completed processing. Each bypass cache is coupled to the input and the output of one of the sections of the processing pipeline so that results of a transaction from that section can be written into or read from the bypass cache as soon as that transaction has been completely processed through that section. With such a configuration, more transactions can be processed by the processing pipeline in a shorter amount of time. This is especially true for very deep pipelines.
摘要翻译：处理流水线采用一个或多个旁路高速缓存，以便在先前交易完成处理之前处理取决于先前交易的结果的交易。每个旁路缓存被耦合到处理流水线中的一个部分的输入和输出，使得一旦该事务已经通过该事务完全处理，则该部分的事务的结果可以被写入或从旁路缓存中读取部分。通过这样的配置，可以在更短的时间内由处理流水线处理更多的事务。对于非常深的管道尤其如此。

10. 发明申请

US20110072244A1 Credit-Based Streaming Multiprocessor Warp Scheduling 有权
标题翻译：基于信用流的多处理器整流器调度
公开(公告)号：US20110072244A1
公开(公告)日：2011-03-24
申请号：US12885299
申请日：2010-09-17
申请人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
发明人： John Erik Lindholm , Brett W. Coon , Jered Wierzbicki , Robert J. Stoll , Stuart F. Oberman
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution.
摘要翻译：本发明的一个实施例提出了一种用于确保高速缓存访问指令被调度用于在多线程系统中执行以提高高速缓存位置和系统性能的技术。可以使用基于信用的技术来对组中的每个翘曲的指令调度来控制指令，使得一组经线被均匀地处理。对每个经纱计算信用额度，并且信用额度有助于每个经线的权重。权重用于选择要执行的经线的指令。

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