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1. 发明授权

US07671403B2 P-channel NAND in isolated N-well 有权
标题翻译：隔离N阱中的P沟道NAND
公开(公告)号：US07671403B2
公开(公告)日：2010-03-02
申请号：US11567257
申请日：2006-12-06
申请人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
发明人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.
摘要翻译：一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质。所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第基质。

2. 发明申请

US20080135918A1 P-CHANNEL NAND IN ISOLATED N-WELL 有权
标题翻译： P-CHANNEL NAND在隔离N-WELL中
公开(公告)号：US20080135918A1
公开(公告)日：2008-06-12
申请号：US11567257
申请日：2006-12-06
申请人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
发明人： Wei Zheng , Chi Chang , Mark Randolph , Satoshi Torii
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568
摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.
摘要翻译：一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质。所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第基质。

3. 发明授权

US07167398B1 System and method for erasing a memory cell 有权
标题翻译：擦除存储单元的系统和方法
公开(公告)号：US07167398B1
公开(公告)日：2007-01-23
申请号：US11062641
申请日：2005-02-23
申请人： Zhizheng Liu , Satoshi Torii , Mark Randolph , Yi He
发明人： Zhizheng Liu , Satoshi Torii , Mark Randolph , Yi He
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0475 , G11C16/14 , H01L29/66833 , H01L29/7923
摘要： A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.
摘要翻译：一种方法擦除包括一组存储单元的半导体器件的存储单元。每个存储单元包括一组存储区域。该方法包括：通过单个热孔注入处理确定要擦除第一存储器单元组的存储区域的每个存储区域并擦除第一存储单元的存储区域组。

4. 发明授权

US07492001B2 High K stack for non-volatile memory 有权
标题翻译：高K堆栈用于非易失性存储器
公开(公告)号：US07492001B2
公开(公告)日：2009-02-17
申请号：US11086310
申请日：2005-03-23
申请人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
发明人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
IPC分类号： H01L29/788 , H01L29/72
CPC分类号： H01L29/792 , G11C16/0475 , H01L21/28273 , H01L21/28282
摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.
摘要翻译：存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极形成在电介质材料层上。

5. 发明授权

US07402868B2 System and method for protecting semiconductor devices 有权
标题翻译：用于保护半导体器件的系统和方法
公开(公告)号：US07402868B2
公开(公告)日：2008-07-22
申请号：US10976816
申请日：2004-11-01
申请人： Ihsan Jahed Djomehri , Mark Randolph , Yi He , Wei Zheng
发明人： Ihsan Jahed Djomehri , Mark Randolph , Yi He , Wei Zheng
IPC分类号： H01L23/62
CPC分类号： H01L27/115 , H01L27/0288
摘要： A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.
摘要翻译：半导体存储器件包括一组字线和被配置成在制造半导体存储器件期间消散来自字线组的电流的结构。

6. 发明授权

US07855114B2 High K stack for non-volatile memory 有权
标题翻译：高K堆栈用于非易失性存储器
公开(公告)号：US07855114B2
公开(公告)日：2010-12-21
申请号：US12351553
申请日：2009-01-09
申请人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
发明人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
IPC分类号： H01L21/336 , H01L29/778
CPC分类号： H01L29/792 , G11C16/0475 , H01L21/28273 , H01L21/28282
摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.
摘要翻译：存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极形成在电介质材料层上。

7. 发明授权

US07750407B2 Strapping contact for charge protection 有权
标题翻译：带式触点用于充电保护
公开(公告)号：US07750407B2
公开(公告)日：2010-07-06
申请号：US11612265
申请日：2006-12-18
申请人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
发明人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
IPC分类号： H01L29/76
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.
摘要翻译：半导体器件包括衬底和形成在衬底上的存储单元。存储单元包括字线。半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

8. 发明授权

US08404541B2 Strapping contact for charge protection 有权
标题翻译：带式触点用于充电保护
公开(公告)号：US08404541B2
公开(公告)日：2013-03-26
申请号：US12790578
申请日：2010-05-28
申请人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
发明人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
IPC分类号： H01L21/8247
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.
摘要翻译：半导体器件包括衬底和形成在衬底上的存储单元。存储单元包括字线。半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

9. 发明申请

US20080151590A1 METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING 有权
标题翻译：用于保护过程诱发电荷的方法和装置
公开(公告)号：US20080151590A1
公开(公告)日：2008-06-26
申请号：US11614053
申请日：2006-12-20
申请人： David M. Rogers , Mimi X. Qian , Kwadwo A. Appiah , Mark Randolph , Michael A. VanBuskirk , Tazrien Kamal , Hiroyuki Kinoshita , Yi He , Wei Zheng
发明人： David M. Rogers , Mimi X. Qian , Kwadwo A. Appiah , Mark Randolph , Michael A. VanBuskirk , Tazrien Kamal , Hiroyuki Kinoshita , Yi He , Wei Zheng
IPC分类号： H01L23/60 , G11C5/00
CPC分类号： H01L21/768 , G11C8/08 , G11C8/14 , H01L27/0248 , H01L29/66477 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).
摘要翻译：用于改善电荷耗散保护的半导体器件（400）包括衬底（426），半导体或导电材料层（406），一个或多个薄膜器件（408）和电荷通道器件（414）。薄膜器件（408）连接到半导体或导电层（406），并且电荷通道器件（414）耦合到薄膜器件（408）和衬底（426），并提供来自薄的薄膜器件（408）到衬底（426）以将电荷从半导体/导电层（406）耗散到衬底（426）。

10. 发明申请

US20060216888A1 High K stack for non-volatile memory 有权
公开(公告)号：US20060216888A1
公开(公告)日：2006-09-28
申请号：US11086310
申请日：2005-03-23
申请人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
发明人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0475 , H01L21/28273 , H01L21/28282
摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

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