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1. 发明授权

US08610181B2 V-groove source/drain MOSFET and process for fabricating same 有权
标题翻译： V沟槽源极/漏极MOSFET及其制造工艺
公开(公告)号：US08610181B2
公开(公告)日：2013-12-17
申请号：US13624251
申请日：2012-09-21
申请人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
发明人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/085
CPC分类号： H01L21/823425 , H01L21/823481 , H01L21/84 , H01L29/045 , H01L29/41733 , H01L29/458 , H01L29/66772
摘要： A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure.
摘要翻译：一种结构包括在衬底的硅表面上至少包含第一和第二相邻栅极结构的衬底和形成在第一和第二相邻栅极结构之间的V形沟槽中的硅化物源/漏极区。形成在V形槽中的硅化物源极/漏极区域基本上从第一栅极结构的边缘延伸到第二栅极结构的相对边缘。

2. 发明授权

US08603868B2 V-groove source/drain MOSFET and process for fabricating same 有权
标题翻译： V沟槽源极/漏极MOSFET及其制造工艺
公开(公告)号：US08603868B2
公开(公告)日：2013-12-10
申请号：US13329604
申请日：2011-12-19
申请人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
发明人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L21/782
CPC分类号： H01L21/823425 , H01L21/823481 , H01L21/84 , H01L29/045 , H01L29/41733 , H01L29/458 , H01L29/66772
摘要： A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.
摘要翻译：一种方法包括在衬底的硅表面上提供至少包含第一和第二相邻栅极结构的衬底; 蚀刻通过所述第一和第二相邻栅极结构之间的所述硅表面的V形槽，其中所述V形槽基本上从所述第一栅极结构的边缘延伸到所述第二栅极结构的相对边缘; 将源极/漏极区域注入到V形沟槽中; 并且将植入的源极/漏极区域硅化。蚀刻步骤优选通过使用停止在硅衬底（例如，SOI层）的Si（111）平面上的基于HCl的化学气相蚀刻（CVE）进行。还公开了根据该方法制造的包含FET的结构。

3. 发明申请

US20130153971A1 V-GROOVE SOURCE/DRAIN MOSFET AND PROCESS FOR FABRICATING SAME 有权
标题翻译： V沟道源/漏极MOSFET及其制造方法
公开(公告)号：US20130153971A1
公开(公告)日：2013-06-20
申请号：US13329604
申请日：2011-12-19
申请人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
发明人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L21/823425 , H01L21/823481 , H01L21/84 , H01L29/045 , H01L29/41733 , H01L29/458 , H01L29/66772
摘要： A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.
摘要翻译：一种方法包括在衬底的硅表面上提供至少包含第一和第二相邻栅极结构的衬底; 蚀刻通过所述第一和第二相邻栅极结构之间的所述硅表面的V形槽，其中所述V形槽基本上从所述第一栅极结构的边缘延伸到所述第二栅极结构的相对边缘; 将源极/漏极区域注入到V形沟槽中; 并且将植入的源极/漏极区域硅化。蚀刻步骤优选通过使用在硅衬底（例如，SOI层）的Si（111）平面上停止的基于HCl的化学气相蚀刻（CVE）进行。还公开了根据该方法制造的包含FET的结构。

4. 发明授权

US08617957B1 Fin bipolar transistors having self-aligned collector and emitter regions 失效
标题翻译：鳍状双极晶体管具有自对准的集电极和发射极区域
公开(公告)号：US08617957B1
公开(公告)日：2013-12-31
申请号：US13607877
申请日：2012-09-10
申请人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
发明人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
IPC分类号： H01L21/331
CPC分类号： H01L29/42304 , H01L29/1008 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735 , H01L29/785
摘要： A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.
摘要翻译：一种制造双极晶体管器件的方法。该方法包括以下步骤：提供其上具有硅层的SOI衬底; 在硅层上平版印刷鳍状硬掩模; 将虚拟接触线放置在图案化翅片硬掩模的中心部分上; 掺杂集电极/发射极区域; 在所述集电极区域和所述发射极区域上沉积填充层; 去除虚拟接触线以露出沟槽和图案化散热片硬掩模的中心部分; 在除去虚拟接触线的步骤之后，通过在沟槽内去除未被图案化翅片硬掩模的中心部分覆盖的硅层的一部分来形成翅片形基底区域; 掺杂鳍片状基底区域; 以及通过在所述鳍状基极区域上的接触线材料填充所述沟槽而形成接触线，其中所述集电极/发射极区域与所述接触线自对准。

5. 发明申请

US20140073106A1 LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY 审中-公开
标题翻译：横向双极晶体管和CMOS混合技术
公开(公告)号：US20140073106A1
公开(公告)日：2014-03-13
申请号：US13610961
申请日：2012-09-12
申请人： Josephine B. Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L21/331
CPC分类号： H01L29/66265 , H01L21/84 , H01L29/6625 , H01L29/7317
摘要： A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.
摘要翻译：一种形成横向双极晶体管的方法。该方法包括形成具有底部衬底层的绝缘体上硅（SOI）衬底，在衬底层顶部上的掩埋氧化物层（BOX）以及BOX层顶部上的绝缘体上硅（SOI）层，形成在绝缘体上硅层的顶部设置虚拟栅极和间隔物，用正离子或负离子掺杂SOI层，使用化学机械平面化（CMP）沉积层间电介质（ILD）以平坦化ILD，去除伪栅极，从而形成栅极沟槽，其显示虚拟栅极的基极，掺杂伪栅极基底，在SOI层的顶部上沉积多晶硅层并进入栅极沟槽，蚀刻多晶硅层，使得其仅覆盖伪栅极基极，以及应用自对准硅化物工艺。

6. 发明授权

US08618636B1 Fin bipolar transistors having self-aligned collector and emitter regions 有权
公开(公告)号：US08618636B1
公开(公告)日：2013-12-31
申请号：US13609615
申请日：2012-09-11
申请人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
发明人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
IPC分类号： H01L29/66
CPC分类号： H01L29/42304 , H01L29/1008 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735 , H01L29/785
摘要： A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.

7. 发明申请

US20120256242A1 SEMICONDUCTOR NANOWIRE STRUCTURE REUSING SUSPENSION PADS 有权
标题翻译：半导体纳米结构复原悬挂垫
公开(公告)号：US20120256242A1
公开(公告)日：2012-10-11
申请号：US13080390
申请日：2011-04-05
申请人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/86 , B82Y99/00 , B82Y40/00
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
摘要翻译：提供一种集成电路装置，其包括形成在绝缘体基板上的第一和第二绝缘体上硅（SOI）焊盘，第一和第二SOI焊盘中的每一个包括形成在其上的有源区，悬挂在第一和第二SOI之间的纳米线绝缘体衬底上的衬垫，沿着纳米线可操作地设置的一个或多个场效应晶体管（FET）和可操作地设置在形成在每个第一和第二SOI衬垫上的相应有源区域中的至少一个上的平面器件。

8. 发明申请

US20170194509A1 WIRE-LAST GATE-ALL-AROUND NANOWIRE FET 审中-公开
公开(公告)号：US20170194509A1
公开(公告)日：2017-07-06
申请号：US15180314
申请日：2016-06-13
申请人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L29/423 , H01L29/66 , H01L29/06
CPC分类号： H01L29/78696 , H01L21/0217 , H01L21/02381 , H01L21/02532 , H01L21/30604 , H01L21/324 , H01L29/0673 , H01L29/165 , H01L29/401 , H01L29/42376 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/775 , H01L29/78618
摘要： A nanowire field effect transistor (FET) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate. A gate region is interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate. A plurality of nanowires are formed only in the gate region. The nanowires are suspended above the semiconductor substrate and define gate channels of the nanowire FET device. A gate structure includes a gate electrode formed in the gate region such that the gate electrode contacts an entire surface of each nanowire.

9. 发明授权

US08853790B2 Semiconductor nanowire structure reusing suspension pads 有权
标题翻译：半导体纳米线结构重用悬挂垫
公开(公告)号：US08853790B2
公开(公告)日：2014-10-07
申请号：US13080390
申请日：2011-04-05
申请人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L51/48 , H01L29/786 , H01L27/12 , H01L29/06 , B82Y10/00 , H01L29/423 , H01L21/84
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
摘要翻译：提供一种集成电路装置，其包括形成在绝缘体基板上的第一和第二绝缘体上硅（SOI）焊盘，第一和第二SOI焊盘中的每一个包括形成在其上的有源区，悬挂在第一和第二SOI之间的纳米线绝缘体衬底上的衬垫，沿着纳米线可操作地设置的一个或多个场效应晶体管（FET）和可操作地设置在形成在每个第一和第二SOI衬垫上的相应有源区域中的至少一个上的平面器件。

10. 发明授权

US08822278B2 Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure 有权
标题翻译：通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构
公开(公告)号：US08822278B2
公开(公告)日：2014-09-02
申请号：US13434128
申请日：2012-03-29
申请人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided. A plurality of active areas is formed in the wafer using STI. A plurality of gate stacks is formed on the wafer, wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area. Spacers are formed on opposite sides of the gate stacks. An angled implant is performed into the source side of the given active area. A FET device is also provided.
摘要翻译：提供了非对称FET器件及其制造方法，其采用可变间距栅极。一方面，一种用于制造FET器件的方法包括以下步骤。提供晶片。使用STI在晶片中形成多个有效区域。在晶片上形成多个栅极堆叠，其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少给定的一个有源区域，给定的源极侧的栅极到栅极间隔有源面积大于给定有源区域的漏极侧上的栅极至栅极间距。隔板形成在栅极堆叠的相对侧上。在给定活动区域的源侧执行成角度的植入物。还提供了FET器件。

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